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Commit 1dff88d1 authored by Eric Kooistra's avatar Eric Kooistra
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Apply wait between tb_end and ASSERT FAILURE.

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libraries/technology/mac_10g/tb_tech_mac_10g_simulation_end.vhd
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...@@ -57,6 +57,7 @@ BEGIN ...@@ -57,6 +57,7 @@ BEGIN
-- Stop the simulation -- Stop the simulation
tb_end <= '1'; tb_end <= '1';
proc_common_wait_some_cycles(clk, 1);
IF g_tb_end=FALSE THEN IF g_tb_end=FALSE THEN
REPORT "Tb simulation finished." SEVERITY NOTE; REPORT "Tb simulation finished." SEVERITY NOTE;
ELSE ELSE
......
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