From 1dff88d1a2da0e0fcd5bfcd96591bae4a6b87746 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Wed, 4 May 2016 11:02:40 +0000
Subject: [PATCH] Apply wait between tb_end and ASSERT FAILURE.
---
libraries/technology/mac_10g/tb_tech_mac_10g_simulation_end.vhd | 1 +
1 file changed, 1 insertion(+)
diff --git a/libraries/technology/mac_10g/tb_tech_mac_10g_simulation_end.vhd b/libraries/technology/mac_10g/tb_tech_mac_10g_simulation_end.vhd
index 8c4e47d9c0..e51c3cc397 100644
--- a/libraries/technology/mac_10g/tb_tech_mac_10g_simulation_end.vhd
+++ b/libraries/technology/mac_10g/tb_tech_mac_10g_simulation_end.vhd
@@ -57,6 +57,7 @@ BEGIN
-- Stop the simulation
tb_end <= '1';
+ proc_common_wait_some_cycles(clk, 1);
IF g_tb_end=FALSE THEN
REPORT "Tb simulation finished." SEVERITY NOTE;
ELSE
--
GitLab