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Commit 19c4e383 authored by Daniel van der Schuur's avatar Daniel van der Schuur
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-Added pipeline to add 4 cycles of delay (relative to snk_in.sync)

before copying DP RAM to MM RAM;
-Changed the RAM block from cr_cw to crw_cw to allow overwrite on the
MM side (via Python);
-Added option to tb_mmp_st_histogram to introduce inconsistent
(long,short,long,short,...) sync intervals such as is the case in LOFAR.
-tb_mmp_st_histogram now shows errors due to the inconsistent sync
interval.
parent d605320a
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