diff --git a/libraries/dsp/st/src/vhdl/mmp_st_histogram.vhd b/libraries/dsp/st/src/vhdl/mmp_st_histogram.vhd
index 02b5005874fdec28e95da2cd3e6a09bb91cdc231..8720e9a5dc10137f5d3659cf6ce4474c86847b07 100644
--- a/libraries/dsp/st/src/vhdl/mmp_st_histogram.vhd
+++ b/libraries/dsp/st/src/vhdl/mmp_st_histogram.vhd
@@ -134,37 +134,51 @@ BEGIN
-- . How do we get the st_histogram RAM contents into the RAMs below?
-- . DPRAM -> read>write process -> MM RAM
-------------------------------------------------------------------------------
- gen_common_ram_cr_cw : FOR i IN 0 TO g_nof_instances-1 GENERATE
- u_common_ram_cr_cw : ENTITY common_lib.common_ram_cr_cw
+ gen_common_ram_crw_cw : FOR i IN 0 TO g_nof_instances-1 GENERATE
+ u_common_ram_crw_cw : ENTITY common_lib.common_ram_crw_cw
GENERIC MAP (
g_technology => c_tech_select_default,
g_ram => c_ram,
g_init_file => "UNUSED"
)
PORT MAP (
- wr_clk => dp_clk,
- wr_rst => dp_rst,
- wr_clken => '1',
- wr_en => wr_copi_arr(i).wr,
- wr_adr => wr_copi_arr(i).address(c_ram_adr_w-1 DOWNTO 0),
- wr_dat => wr_copi_arr(i).wrdata(c_ram_dat_w-1 DOWNTO 0),
- rd_clk => mm_clk,
- rd_rst => mm_rst,
- rd_clken => '1',
- rd_en => ram_copi_arr(i).rd,
- rd_adr => ram_copi_arr(i).address(c_ram_adr_w-1 DOWNTO 0),
- rd_dat => ram_cipo_arr(i).rddata(c_ram_dat_w-1 DOWNTO 0),
- rd_val => ram_cipo_arr(i).rdval
- );
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ mm_wr_en => ram_copi_arr(i).wr,
+ mm_wr_dat => ram_copi_arr(i).wrdata(c_ram_dat_w-1 DOWNTO 0),
+ mm_adr => ram_copi_arr(i).address(c_ram_adr_w-1 DOWNTO 0),
+ mm_rd_en => ram_copi_arr(i).rd,
+ mm_rd_dat => ram_cipo_arr(i).rddata(c_ram_dat_w-1 DOWNTO 0),
+ mm_rd_val => ram_cipo_arr(i).rdval,
+
+ st_clk => dp_clk,
+ st_rst => dp_rst,
+ st_wr_en => wr_copi_arr(i).wr,
+ st_adr => wr_copi_arr(i).address(c_ram_adr_w-1 DOWNTO 0),
+ st_wr_dat => wr_copi_arr(i).wrdata(c_ram_dat_w-1 DOWNTO 0)
+ );
END GENERATE;
-
+
-------------------------------------------------------------------------------
- -- Logic to move st_histogram RAM contents into the dual clock RAM above
+ -- Use snk_in Sync pulse to trigger RAM copy
+ -- . use pipeline>=st_histogram I/O latency - don't copy too soon (clash with clear)
-------------------------------------------------------------------------------
- -- Use only the status signal of st_histogram instance 0
- ram_fill <= snk_in_arr(0).sync;
+ u_common_pipeline_sl : ENTITY common_lib.common_pipeline_sl
+ GENERIC MAP (
+ g_pipeline => 4
+ )
+ PORT MAP (
+ clk => dp_clk,
+ rst => dp_rst,
+ in_dat => snk_in_arr(0).sync, -- Use only the status signal of st_histogram instance 0
+ out_dat => ram_fill
+ );
+
+ -------------------------------------------------------------------------------
+ -- Logic to move st_histogram RAM contents into the dual clock RAM above
+ -------------------------------------------------------------------------------
-- Keep track of ram_filling status and ram_address (used for reading and writing)
nxt_ram_filling <= '0' WHEN TO_UINT(ram_address)=c_addr_high ELSE '1' WHEN ram_fill='1' ELSE ram_filling;
nxt_ram_address <= (OTHERS=>'0') WHEN ram_filling='0' ELSE INCR_UVEC(ram_address, 1) WHEN ram_filling='1' ELSE ram_address;
diff --git a/libraries/dsp/st/tb/vhdl/tb_mmp_st_histogram.vhd b/libraries/dsp/st/tb/vhdl/tb_mmp_st_histogram.vhd
index 57f34d26041b1cc6357e74c9acb708843ef50544..4cd2c9549e8b841814c35b23db32ebdfd509170a 100644
--- a/libraries/dsp/st/tb/vhdl/tb_mmp_st_histogram.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_mmp_st_histogram.vhd
@@ -53,8 +53,9 @@ ENTITY tb_mmp_st_histogram IS
g_data_w : NATURAL := 14;
g_nof_bins : NATURAL := 512;
g_nof_data_per_sync : NATURAL := 16384; -- g_nof_data_per_sync/g_nof_bins should be integer so counter data yields the same histogram in each bin
- g_stimuli_mode : STRING := "counter" -- "counter", "dc", "sine" or "random"
- );
+ g_stimuli_mode : STRING := "counter"; -- "counter", "dc", "sine" or "random"
+ g_sync_interval_diff : NATURAL := 64 -- Use non-constant g_nof_data_per_sync: longer (+g_sync_interval_diff), shorter (-g_sync_interval_diff),
+ ); -- longer, shorter, etc. E.g. LOFAR2 uses 200M+-512 samples per sync.
END tb_mmp_st_histogram;
@@ -87,6 +88,7 @@ ARCHITECTURE tb OF tb_mmp_st_histogram IS
SIGNAL stimuli_src_out : t_dp_sosi;
SIGNAL stimuli_src_in : t_dp_siso;
SIGNAL stimuli_done : STD_LOGIC;
+ SIGNAL long_sync_interval : BOOLEAN := TRUE;
----------------------------------------------------------------------------
-- st_histogram
@@ -129,6 +131,7 @@ BEGIN
-- Generate g_nof_sync packets of g_nof_data_per_sync words
p_generate_packets : PROCESS
VARIABLE v_sosi : t_dp_sosi := c_dp_sosi_rst;
+ VARIABLE v_nof_data_per_sync : NATURAL;
BEGIN
stimuli_done <= '0';
stimuli_src_out <= c_dp_sosi_rst;
@@ -136,10 +139,19 @@ BEGIN
proc_common_wait_some_cycles(dp_clk, 5);
FOR I IN 0 TO g_nof_sync-1 LOOP
+ -- Optionally replace equal period lengths with: shorter, longer, shorter, longer, ...
+ long_sync_interval <= NOT long_sync_interval;
+ v_nof_data_per_sync := g_nof_data_per_sync;
+ IF long_sync_interval THEN
+ v_nof_data_per_sync := g_nof_data_per_sync+g_sync_interval_diff;
+ ELSE --Short interval
+ v_nof_data_per_sync := g_nof_data_per_sync-g_sync_interval_diff;
+ END IF;
+
v_sosi.sync := '1';
v_sosi.data := RESIZE_DP_DATA(v_sosi.data(g_data_w-1 DOWNTO 0)); -- wrap when >= 2**g_data_w
-- Generate a block of counter data
- proc_dp_gen_block_data(g_data_w, TO_UINT(v_sosi.data), g_nof_data_per_sync, TO_UINT(v_sosi.channel), TO_UINT(v_sosi.err), v_sosi.sync, v_sosi.bsn, dp_clk, stimuli_en, stimuli_src_in, stimuli_src_out);
+ proc_dp_gen_block_data(g_data_w, TO_UINT(v_sosi.data), v_nof_data_per_sync, TO_UINT(v_sosi.channel), TO_UINT(v_sosi.err), v_sosi.sync, v_sosi.bsn, dp_clk, stimuli_en, stimuli_src_in, stimuli_src_out);
END LOOP;
stimuli_done <= '1';
@@ -207,10 +219,17 @@ BEGIN
BEGIN
st_histogram_ram_copi.wr <= '0';
FOR i IN 0 TO g_nof_sync-1 LOOP
+ -- mmp_st_histogram will start copying DP RAM contents to MM RAM 4 cyles after sync
proc_common_wait_until_high(dp_clk, stimuli_src_out.sync);
- proc_common_wait_some_cycles(dp_clk, 10);
+ proc_common_wait_some_cycles(dp_clk, 4);
+
+ -- Wait until copying the bins completes
+ proc_common_wait_some_cycles(dp_clk, 512);
+
+ -- Start MM reading the bins after some safety cycles
+ proc_common_wait_some_cycles(mm_clk, 20);
FOR j IN 0 TO g_nof_bins-1 LOOP
- proc_mem_mm_bus_rd(j, dp_clk, st_histogram_ram_copi);
+ proc_mem_mm_bus_rd(j, mm_clk, st_histogram_ram_copi);
END LOOP;
END LOOP;
WAIT;
@@ -230,7 +249,7 @@ BEGIN
sum_of_bins <= 0;
proc_common_wait_until_high(dp_clk, stimuli_src_out.sync);
FOR j IN 0 TO g_nof_bins-1 LOOP
- proc_common_wait_until_high(dp_clk, histogram_valid);
+ proc_common_wait_until_high(mm_clk, histogram_valid);
IF i=0 THEN -- Sync period 0: we expect RAM to contain zeros
ASSERT histogram_data=0 REPORT "RAM contains wrong bin count (expected 0, actual " & INTEGER'IMAGE(histogram_data) & ")" SEVERITY ERROR;
ELSE -- Sync period 1 onwards
@@ -249,7 +268,7 @@ BEGIN
END IF;
END IF;
sum_of_bins<=sum_of_bins+histogram_data; -- Keep the sum of all bins
- WAIT FOR 5 ns;
+ proc_common_wait_some_cycles(mm_clk, 1);
END LOOP;
-- Check the sum of all bins