libraries/dsp/st/src/vhdl/mmp_st_histogram.vhd · 19c4e383605695c296078fee3108216d58b12c01 · RTSD / HDL

3 years ago

-Added pipeline to add 4 cycles of delay (relative to snk_in.sync) · 19c4e383

Daniel van der Schuur authored 3 years ago

before copying DP RAM to MM RAM;
-Changed the RAM block from cr_cw to crw_cw to allow overwrite on the
MM side (via Python);
-Added option to tb_mmp_st_histogram to introduce inconsistent
(long,short,long,short,...) sync intervals such as is the case in LOFAR.
-tb_mmp_st_histogram now shows errors due to the inconsistent sync
interval.

19c4e383

History

-Added pipeline to add 4 cycles of delay (relative to snk_in.sync)

Daniel van der Schuur authored 3 years ago

before copying DP RAM to MM RAM;
-Changed the RAM block from cr_cw to crw_cw to allow overwrite on the
MM side (via Python);
-Added option to tb_mmp_st_histogram to introduce inconsistent
(long,short,long,short,...) sync intervals such as is the case in LOFAR.
-tb_mmp_st_histogram now shows errors due to the inconsistent sync
interval.

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