Add missing common_adder_tree_im_sum in sensitivity list of p_src_out.

libraries/base/dp/src/vhdl/dp_complex_add.vhd

@@ -106,7 +106,7 @@ BEGIN
     sum    => common_adder_tree_im_sum
   );   
 
-  p_src_out : PROCESS(snk_in_pipe, common_adder_tree_re_sum)
+  p_src_out : PROCESS(snk_in_pipe, common_adder_tree_re_sum, common_adder_tree_im_sum)
   BEGIN
     src_out <= snk_in_pipe;
     src_out.re <= RESIZE_DP_DSP_DATA(common_adder_tree_re_sum(c_common_adder_tree_sum_w-1 DOWNTO 0));
@@ -117,6 +117,7 @@ BEGIN
   -- Forward the other snk_in fields with the correct latency
   -----------------------------------------------------------------------------
 
+  -- All g_nof_inputs have same, so use other fields from input 0 for all
   snk_in <= snk_in_arr(0);
 
   u_dp_pipeline : ENTITY work.dp_pipeline