Pipeline all snk_in sosi fields for output, instead of only the valid.

libraries/base/dp/src/vhdl/dp_complex_add.vhd

@@ -52,8 +52,13 @@ END dp_complex_add;
 ARCHITECTURE str OF dp_complex_add IS
 
   CONSTANT c_pipeline                : NATURAL := 1;
+  CONSTANT c_pipeline_adder_tree     : NATURAL := c_pipeline*ceil_log2(g_nof_inputs);
+
   CONSTANT c_common_adder_tree_sum_w : NATURAL := g_data_w + ceil_log2(g_nof_inputs);
 
+  SIGNAL snk_in                      : t_dp_sosi;
+  SIGNAL snk_in_pipe                 : t_dp_sosi;
+
   SIGNAL common_adder_tree_re_in_dat : STD_LOGIC_VECTOR(g_nof_inputs*g_data_w-1 DOWNTO 0);
   SIGNAL common_adder_tree_im_in_dat : STD_LOGIC_VECTOR(g_nof_inputs*g_data_w-1 DOWNTO 0);
 
@@ -101,22 +106,30 @@ BEGIN
     sum    => common_adder_tree_im_sum
   );   
 
-  src_out.re <= RESIZE_DP_DSP_DATA(common_adder_tree_re_sum(c_common_adder_tree_sum_w-1 DOWNTO 0));
-  src_out.im <= RESIZE_DP_DSP_DATA(common_adder_tree_im_sum(c_common_adder_tree_sum_w-1 DOWNTO 0));
+  p_src_out : PROCESS(snk_in_pipe, common_adder_tree_re_sum)
+  BEGIN
+    src_out <= snk_in_pipe;
+    src_out.re <= RESIZE_DP_DSP_DATA(common_adder_tree_re_sum(c_common_adder_tree_sum_w-1 DOWNTO 0));
+    src_out.im <= RESIZE_DP_DSP_DATA(common_adder_tree_im_sum(c_common_adder_tree_sum_w-1 DOWNTO 0));
+  END PROCESS;
 
   -----------------------------------------------------------------------------
-  -- Forward the input valid with the correct latency
+  -- Forward the other snk_in fields with the correct latency
   -----------------------------------------------------------------------------
-  u_common_pipeline_sl : ENTITY common_lib.common_pipeline_sl
-   GENERIC MAP (
-     g_pipeline  => c_pipeline*ceil_log2(g_nof_inputs)
-   )
-   PORT MAP (
-     rst     => rst,
-     clk     => clk,
- 
-     in_dat  => snk_in_arr(0).valid,
-     out_dat => src_out.valid
-   );
- 
+
+  snk_in <= snk_in_arr(0);
+
+  u_dp_pipeline : ENTITY work.dp_pipeline
+  GENERIC MAP (
+    g_pipeline   => c_pipeline_adder_tree
+  )
+  PORT MAP (
+    rst     => rst,
+    clk     => clk,
+    -- ST sink
+    snk_in  => snk_in,
+    -- ST source
+    src_out => snk_in_pipe
+  );
+
 END str;