unb2c ip

libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_dc_mixed_widths.qsys

-<?xml version="1.0" encoding="UTF-8"?>
-<system name="ip_arria10_e2sg_fifo_dc_mixed_widths">
- <component
-   name="$${FILENAME}"
-   displayName="$${FILENAME}"
-   version="1.0"
-   description=""
-   tags="AUTHORSHIP=Intel Corporation"
-   categories="System"
-   tool="QsysStandard" />
- <parameter name="bonusData"><![CDATA[bonusData 
-{
-   element $system
-   {
-   }
-   element ip_arria10_fifo_dc_mixed_widths
-   {
-      datum _sortIndex
-      {
-         value = "0";
-         type = "int";
-      }
-   }
-}
-]]></parameter>
- <parameter name="device" value="10AX115U3F45E2SG" />
- <parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="2" />
- <parameter name="fabricMode" value="QSYS" />
- <parameter name="generateLegacySim" value="false" />
- <parameter name="generationId" value="0" />
- <parameter name="globalResetBus" value="false" />
- <parameter name="hdlLanguage" value="VERILOG" />
- <parameter name="hideFromIPCatalog" value="false" />
- <parameter name="lockedInterfaceDefinition" value="" />
- <parameter name="sopcBorderPoints" value="false" />
- <parameter name="systemHash" value="0" />
- <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
-    <connPtSystemInfos/>
-</systemInfosDefinition>]]></parameter>
- <parameter name="systemScripts" value="" />
- <parameter name="testBenchDutName" value="" />
- <parameter name="timeStamp" value="0" />
- <parameter name="useTestBenchNamingPattern" value="false" />
- <instanceScript></instanceScript>
- <interface
-   name="fifo_input"
-   internal="ip_arria10_fifo_dc_mixed_widths.fifo_input"
-   type="conduit"
-   dir="end">
-  <port name="aclr" internal="aclr" />
-  <port name="data" internal="data" />
-  <port name="rdclk" internal="rdclk" />
-  <port name="rdreq" internal="rdreq" />
-  <port name="wrclk" internal="wrclk" />
-  <port name="wrreq" internal="wrreq" />
- </interface>
- <interface
-   name="fifo_output"
-   internal="ip_arria10_fifo_dc_mixed_widths.fifo_output"
-   type="conduit"
-   dir="end">
-  <port name="q" internal="q" />
-  <port name="rdempty" internal="rdempty" />
-  <port name="rdusedw" internal="rdusedw" />
-  <port name="wrfull" internal="wrfull" />
-  <port name="wrusedw" internal="wrusedw" />
- </interface>
- <module
-   name="ip_arria10_fifo_dc_mixed_widths"
-   kind="fifo"
-   version="19.1"
-   enabled="1"
-   autoexport="1">
-  <parameter name="DEVICE_FAMILY" value="Arria 10" />
-  <parameter name="GUI_AlmostEmpty" value="false" />
-  <parameter name="GUI_AlmostEmptyThr" value="-1" />
-  <parameter name="GUI_AlmostFull" value="false" />
-  <parameter name="GUI_AlmostFullThr" value="-1" />
-  <parameter name="GUI_CLOCKS_ARE_SYNCHRONIZED" value="0" />
-  <parameter name="GUI_Clock" value="4" />
-  <parameter name="GUI_DISABLE_DCFIFO_EMBEDDED_TIMING_CONSTRAINT" value="true" />
-  <parameter name="GUI_Depth" value="256" />
-  <parameter name="GUI_ENABLE_ECC" value="false" />
-  <parameter name="GUI_Empty" value="true" />
-  <parameter name="GUI_Full" value="true" />
-  <parameter name="GUI_LE_BasedFIFO" value="false" />
-  <parameter name="GUI_LegacyRREQ" value="1" />
-  <parameter name="GUI_MAX_DEPTH" value="Auto" />
-  <parameter name="GUI_MAX_DEPTH_BY_9" value="false" />
-  <parameter name="GUI_OVERFLOW_CHECKING" value="false" />
-  <parameter name="GUI_Optimize" value="1" />
-  <parameter name="GUI_Optimize_max" value="1" />
-  <parameter name="GUI_RAM_BLOCK_TYPE" value="Auto" />
-  <parameter name="GUI_TESTBENCH" value="false" />
-  <parameter name="GUI_UNDERFLOW_CHECKING" value="false" />
-  <parameter name="GUI_UsedW" value="true" />
-  <parameter name="GUI_Width" value="8" />
-  <parameter name="GUI_dc_aclr" value="true" />
-  <parameter name="GUI_delaypipe" value="5" />
-  <parameter name="GUI_diff_widths" value="true" />
-  <parameter name="GUI_msb_usedw" value="false" />
-  <parameter name="GUI_output_width" value="16" />
-  <parameter name="GUI_read_aclr_synch" value="false" />
-  <parameter name="GUI_rsEmpty" value="true" />
-  <parameter name="GUI_rsFull" value="false" />
-  <parameter name="GUI_rsUsedW" value="true" />
-  <parameter name="GUI_sc_aclr" value="false" />
-  <parameter name="GUI_sc_sclr" value="false" />
-  <parameter name="GUI_synStage" value="3" />
-  <parameter name="GUI_write_aclr_synch" value="true" />
-  <parameter name="GUI_wsEmpty" value="false" />
-  <parameter name="GUI_wsFull" value="true" />
-  <parameter name="GUI_wsUsedW" value="true" />
- </module>
-</system>

libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/hdllib.cfg

@@ -20,5 +20,5 @@ quartus_qip_files =
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
-    ip_arria10_e2sg_asmi_parallel.qsys
+    ip_arria10_e2sg_asmi_parallel.ip
 

libraries/technology/ip_arria10_e2sg/flash/remote_update/hdllib.cfg

@@ -20,5 +20,5 @@ quartus_qip_files =
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
-    ip_arria10_e2sg_remote_update.qsys
+    ip_arria10_e2sg_remote_update.ip
 

libraries/technology/ip_arria10_e2sg/fractional_pll_clk125/hdllib.cfg

@@ -20,5 +20,5 @@ quartus_qip_files =
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
-    ip_arria10_e2sg_fractional_pll_clk125.qsys
+    ip_arria10_e2sg_fractional_pll_clk125.ip
 

libraries/technology/ip_arria10_e2sg/fractional_pll_clk200/hdllib.cfg

@@ -20,5 +20,5 @@ quartus_qip_files =
 
 [generate_ip_libs]
 qsys-generate_ip_files = 
-    ip_arria10_e2sg_fractional_pll_clk200.qsys
+    ip_arria10_e2sg_fractional_pll_clk200.ip