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Commit 12f3c29c authored by Kenneth Hiemstra's avatar Kenneth Hiemstra
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unb2c ip

parent 13fbc962
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2 merge requests!100Removed text for XSub that is now written in Confluence Subband correlator...,!77Resolve L2SDP-37 (merge request)
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libraries/technology/ip_arria10_e2sg/clkbuf_global/hdllib.cfg
+ 1
− 1
View file @ 12f3c29c
......@@ -20,5 +20,5 @@ quartus_qip_files =
[generate_ip_libs]
qsys-generate_ip_files =
ip_arria10_e2sg_clkbuf_global.qsys
ip_arria10_e2sg_clkbuf_global.ip
libraries/technology/ip_arria10_e2sg/clkbuf_global/ip_arria10_e2sg_clkbuf_global.ip 0 → 100644
+ 256
− 0
View file @ 12f3c29c
<?xml version="1.0" ?>
<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
<ipxact:vendor>Intel Corporation</ipxact:vendor>
<ipxact:library>ip_arria10_e2sg_clkbuf_global</ipxact:library>
<ipxact:name>altclkctrl_0</ipxact:name>
<ipxact:version>19.1</ipxact:version>
<ipxact:busInterfaces>
<ipxact:busInterface>
<ipxact:name>altclkctrl_input</ipxact:name>
<ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
<ipxact:abstractionTypes>
<ipxact:abstractionType>
<ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
<ipxact:portMaps>
<ipxact:portMap>
<ipxact:logicalPort>
<ipxact:name>inclk</ipxact:name>
</ipxact:logicalPort>
<ipxact:physicalPort>
<ipxact:name>inclk</ipxact:name>
</ipxact:physicalPort>
</ipxact:portMap>
</ipxact:portMaps>
</ipxact:abstractionType>
</ipxact:abstractionTypes>
<ipxact:slave></ipxact:slave>
<ipxact:parameters>
<ipxact:parameter parameterId="associatedClock" type="string">
<ipxact:name>associatedClock</ipxact:name>
<ipxact:displayName>associatedClock</ipxact:displayName>
<ipxact:value></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="associatedReset" type="string">
<ipxact:name>associatedReset</ipxact:name>
<ipxact:displayName>associatedReset</ipxact:displayName>
<ipxact:value></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="prSafe" type="bit">
<ipxact:name>prSafe</ipxact:name>
<ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
<ipxact:vendorExtensions>
<altera:altera_assignments>
<ipxact:parameters>
<ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
<ipxact:name>ui.blockdiagram.direction</ipxact:name>
<ipxact:value>input</ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
</altera:altera_assignments>
</ipxact:vendorExtensions>
</ipxact:busInterface>
<ipxact:busInterface>
<ipxact:name>altclkctrl_output</ipxact:name>
<ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
<ipxact:abstractionTypes>
<ipxact:abstractionType>
<ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
<ipxact:portMaps>
<ipxact:portMap>
<ipxact:logicalPort>
<ipxact:name>outclk</ipxact:name>
</ipxact:logicalPort>
<ipxact:physicalPort>
<ipxact:name>outclk</ipxact:name>
</ipxact:physicalPort>
</ipxact:portMap>
</ipxact:portMaps>
</ipxact:abstractionType>
</ipxact:abstractionTypes>
<ipxact:slave></ipxact:slave>
<ipxact:parameters>
<ipxact:parameter parameterId="associatedClock" type="string">
<ipxact:name>associatedClock</ipxact:name>
<ipxact:displayName>associatedClock</ipxact:displayName>
<ipxact:value></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="associatedReset" type="string">
<ipxact:name>associatedReset</ipxact:name>
<ipxact:displayName>associatedReset</ipxact:displayName>
<ipxact:value></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="prSafe" type="bit">
<ipxact:name>prSafe</ipxact:name>
<ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
<ipxact:vendorExtensions>
<altera:altera_assignments>
<ipxact:parameters>
<ipxact:parameter parameterId="ui.blockdiagram.direction" type="string">
<ipxact:name>ui.blockdiagram.direction</ipxact:name>
<ipxact:value>output</ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
</altera:altera_assignments>
</ipxact:vendorExtensions>
</ipxact:busInterface>
</ipxact:busInterfaces>
<ipxact:model>
<ipxact:views>
<ipxact:view>
<ipxact:name>QUARTUS_SYNTH</ipxact:name>
<ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
<ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
</ipxact:view>
</ipxact:views>
<ipxact:instantiations>
<ipxact:componentInstantiation>
<ipxact:name>QUARTUS_SYNTH</ipxact:name>
<ipxact:moduleName>altclkctrl</ipxact:moduleName>
<ipxact:fileSetRef>
<ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
</ipxact:fileSetRef>
</ipxact:componentInstantiation>
</ipxact:instantiations>
<ipxact:ports>
<ipxact:port>
<ipxact:name>inclk</ipxact:name>
<ipxact:wire>
<ipxact:direction>in</ipxact:direction>
<ipxact:wireTypeDefs>
<ipxact:wireTypeDef>
<ipxact:typeName>STD_LOGIC</ipxact:typeName>
<ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
</ipxact:wireTypeDef>
</ipxact:wireTypeDefs>
</ipxact:wire>
</ipxact:port>
<ipxact:port>
<ipxact:name>outclk</ipxact:name>
<ipxact:wire>
<ipxact:direction>out</ipxact:direction>
<ipxact:wireTypeDefs>
<ipxact:wireTypeDef>
<ipxact:typeName>STD_LOGIC</ipxact:typeName>
<ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
</ipxact:wireTypeDef>
</ipxact:wireTypeDefs>
</ipxact:wire>
</ipxact:port>
</ipxact:ports>
</ipxact:model>
<ipxact:vendorExtensions>
<altera:entity_info>
<ipxact:vendor>Intel Corporation</ipxact:vendor>
<ipxact:library>ip_arria10_e2sg_clkbuf_global</ipxact:library>
<ipxact:name>altclkctrl</ipxact:name>
<ipxact:version>19.1</ipxact:version>
</altera:entity_info>
<altera:altera_module_parameters>
<ipxact:parameters>
<ipxact:parameter parameterId="DEVICE_FAMILY" type="string">
<ipxact:name>DEVICE_FAMILY</ipxact:name>
<ipxact:displayName>Device Family</ipxact:displayName>
<ipxact:value>Arria 10</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="CLOCK_TYPE" type="int">
<ipxact:name>CLOCK_TYPE</ipxact:name>
<ipxact:displayName>How do you want to use the ALTCLKCTRL?</ipxact:displayName>
<ipxact:value>1</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="NUMBER_OF_CLOCKS" type="int">
<ipxact:name>NUMBER_OF_CLOCKS</ipxact:name>
<ipxact:displayName>How many clock inputs would you like?</ipxact:displayName>
<ipxact:value>1</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="ENA_REGISTER_MODE" type="int">
<ipxact:name>ENA_REGISTER_MODE</ipxact:name>
<ipxact:displayName>How do you want to register the 'ena' port?</ipxact:displayName>
<ipxact:value>1</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="GUI_USE_ENA" type="bit">
<ipxact:name>GUI_USE_ENA</ipxact:name>
<ipxact:displayName>Create 'ena' port to enable or disable the clock network driven by this buffer?</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION" type="bit">
<ipxact:name>USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION</ipxact:name>
<ipxact:displayName>Ensure glitch-free switchover implementation</ipxact:displayName>
<ipxact:value>false</ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
</altera:altera_module_parameters>
<altera:altera_system_parameters>
<ipxact:parameters>
<ipxact:parameter parameterId="device" type="string">
<ipxact:name>device</ipxact:name>
<ipxact:displayName>Device</ipxact:displayName>
<ipxact:value>10AX115U3F45E2SG</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="deviceFamily" type="string">
<ipxact:name>deviceFamily</ipxact:name>
<ipxact:displayName>Device family</ipxact:displayName>
<ipxact:value>Arria 10</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="deviceSpeedGrade" type="string">
<ipxact:name>deviceSpeedGrade</ipxact:name>
<ipxact:displayName>Device Speed Grade</ipxact:displayName>
<ipxact:value>2</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="generationId" type="int">
<ipxact:name>generationId</ipxact:name>
<ipxact:displayName>Generation Id</ipxact:displayName>
<ipxact:value>0</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="bonusData" type="string">
<ipxact:name>bonusData</ipxact:name>
<ipxact:displayName>bonusData</ipxact:displayName>
<ipxact:value>bonusData
{
element altclkctrl_0
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
}
</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
<ipxact:name>hideFromIPCatalog</ipxact:name>
<ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
<ipxact:value>true</ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
<ipxact:name>lockedInterfaceDefinition</ipxact:name>
<ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
<ipxact:value></ipxact:value>
</ipxact:parameter>
<ipxact:parameter parameterId="systemInfos" type="string">
<ipxact:name>systemInfos</ipxact:name>
<ipxact:displayName>systemInfos</ipxact:displayName>
<ipxact:value>&lt;systemInfosDefinition&gt;
&lt;connPtSystemInfos/&gt;
&lt;/systemInfosDefinition&gt;</ipxact:value>
</ipxact:parameter>
</ipxact:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
<altera:interface_mapping altera:name="altclkctrl_input" altera:internal="altclkctrl_0.altclkctrl_input" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="inclk" altera:internal="inclk"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="altclkctrl_output" altera:internal="altclkctrl_0.altclkctrl_output" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="outclk" altera:internal="outclk"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
<altera:altera_has_warnings>false</altera:altera_has_warnings>
<altera:altera_has_errors>false</altera:altera_has_errors>
</ipxact:vendorExtensions>
</ipxact:component>
\ No newline at end of file
libraries/technology/ip_arria10_e2sg/clkbuf_global/ip_arria10_e2sg_clkbuf_global.qsys deleted 100644 → 0
+ 0
− 73
View file @ 13fbc962
<?xml version="1.0" encoding="UTF-8"?>
<system name="ip_arria10_e2sg_clkbuf_global">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
categories="System"
tool="QsysStandard" />
<parameter name="bonusData"><![CDATA[bonusData
{
element $system
{
}
element altclkctrl_0
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
}
]]></parameter>
<parameter name="device" value="10AX115U3F45E2SG" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="1" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
<connPtSystemInfos/>
</systemInfosDefinition>]]></parameter>
<parameter name="systemScripts" value="" />
<parameter name="testBenchDutName" value="" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
name="altclkctrl_input"
internal="altclkctrl_0.altclkctrl_input"
type="conduit"
dir="end">
<port name="inclk" internal="inclk" />
</interface>
<interface
name="altclkctrl_output"
internal="altclkctrl_0.altclkctrl_output"
type="conduit"
dir="end">
<port name="outclk" internal="outclk" />
</interface>
<module
name="altclkctrl_0"
kind="altclkctrl"
version="19.1"
enabled="1"
autoexport="1">
<parameter name="CLOCK_TYPE" value="1" />
<parameter name="DEVICE_FAMILY" value="Arria 10" />
<parameter name="ENA_REGISTER_MODE" value="1" />
<parameter name="GUI_USE_ENA" value="false" />
<parameter name="NUMBER_OF_CLOCKS" value="1" />
<parameter name="USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION" value="false" />
</module>
</system>
libraries/technology/ip_arria10_e2sg/complex_mult/hdllib.cfg
+ 1
− 1
View file @ 12f3c29c
......@@ -20,5 +20,5 @@ quartus_qip_files =
[generate_ip_libs]
qsys-generate_ip_files =
ip_arria10_e2sg_complex_mult.qsys
ip_arria10_e2sg_complex_mult.ip
libraries/technology/ip_arria10_e2sg/complex_mult/ip_arria10_e2sg_complex_mult.qsys deleted 100644 → 0
+ 0
− 122
View file @ 13fbc962
<?xml version="1.0" encoding="UTF-8"?>
<system name="ip_arria10_e2sg_complex_mult">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags="AUTHORSHIP=Intel Corporation /// INTERNAL_COMPONENT=true"
categories="System"
tool="QsysStandard" />
<parameter name="bonusData"><![CDATA[bonusData
{
element $system
{
}
element altmult_complex_0
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
}
]]></parameter>
<parameter name="device" value="10AX115U3F45E2SG" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="2" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="true" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
<connPtSystemInfos/>
</systemInfosDefinition>]]></parameter>
<parameter name="systemScripts" value="" />
<parameter name="testBenchDutName" value="" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface name="aclr" internal="altmult_complex_0.aclr" type="reset" dir="end">
<port name="aclr" internal="aclr" />
</interface>
<interface
name="clock"
internal="altmult_complex_0.clock"
type="clock"
dir="end">
<port name="clock" internal="clock" />
</interface>
<interface name="complex_input" internal="altmult_complex_0.complex_input" />
<interface name="complex_output" internal="altmult_complex_0.complex_output" />
<interface
name="dataa_imag"
internal="altmult_complex_0.dataa_imag"
type="conduit"
dir="end">
<port name="dataa_imag" internal="dataa_imag" />
</interface>
<interface
name="dataa_real"
internal="altmult_complex_0.dataa_real"
type="conduit"
dir="end">
<port name="dataa_real" internal="dataa_real" />
</interface>
<interface
name="datab_imag"
internal="altmult_complex_0.datab_imag"
type="conduit"
dir="end">
<port name="datab_imag" internal="datab_imag" />
</interface>
<interface
name="datab_real"
internal="altmult_complex_0.datab_real"
type="conduit"
dir="end">
<port name="datab_real" internal="datab_real" />
</interface>
<interface name="ena" internal="altmult_complex_0.ena" type="conduit" dir="end">
<port name="ena" internal="ena" />
</interface>
<interface
name="result_imag"
internal="altmult_complex_0.result_imag"
type="conduit"
dir="end">
<port name="result_imag" internal="result_imag" />
</interface>
<interface
name="result_real"
internal="altmult_complex_0.result_real"
type="conduit"
dir="end">
<port name="result_real" internal="result_real" />
</interface>
<module
name="altmult_complex_0"
kind="altmult_complex"
version="19.1.0"
enabled="1"
autoexport="1">
<parameter name="CBX_AUTO_BLACKBOX" value="ALL" />
<parameter name="DEVICE_FAMILY" value="Arria 10" />
<parameter name="GUI_CLEAR_TYPE" value="ACLR" />
<parameter name="GUI_DYNAMIC_COMPLEX" value="false" />
<parameter name="GUI_USE_CLKEN" value="true" />
<parameter name="IMPLEMENTATION_STYLE" value="AUTO" />
<parameter name="PIPELINE" value="3" />
<parameter name="REPRESENTATION_A" value="1" />
<parameter name="REPRESENTATION_B" value="1" />
<parameter name="WIDTH_A" value="18" />
<parameter name="WIDTH_B" value="18" />
<parameter name="WIDTH_RESULT" value="36" />
</module>
</system>
libraries/technology/ip_arria10_e2sg/ddio/hdllib.cfg
+ 2
− 3
View file @ 12f3c29c
......@@ -23,6 +23,5 @@ quartus_qip_files =
[generate_ip_libs]
qsys-generate_ip_files =
ip_arria10_e2sg_ddio_in_1.qsys
ip_arria10_e2sg_ddio_out_1.qsys
ip_arria10_e2sg_ddio_in_1.ip
ip_arria10_e2sg_ddio_out_1.ip
libraries/technology/ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_in_1.ip 0 → 100644
+ 630
− 0
View file @ 12f3c29c
This diff is collapsed.
libraries/technology/ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_in_1.qsys deleted 100644 → 0
+ 0
− 108
View file @ 13fbc962
<?xml version="1.0" encoding="UTF-8"?>
<system name="ip_arria10_e2sg_ddio_in_1">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags="AUTHORSHIP=Intel Corporation"
categories="System"
tool="QsysStandard" />
<parameter name="bonusData"><![CDATA[bonusData
{
element $system
{
}
element ip_arria10_ddio_in_1
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
}
]]></parameter>
<parameter name="device" value="10AX115U3F45E2SG" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="2" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="false" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
<connPtSystemInfos/>
</systemInfosDefinition>]]></parameter>
<parameter name="systemScripts" value="" />
<parameter name="testBenchDutName" value="" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
name="aclr"
internal="ip_arria10_ddio_in_1.aclr"
type="conduit"
dir="end">
<port name="aclr" internal="aclr" />
</interface>
<interface name="ck" internal="ip_arria10_ddio_in_1.ck" type="conduit" dir="end">
<port name="inclock" internal="inclock" />
</interface>
<interface
name="dataout_h"
internal="ip_arria10_ddio_in_1.dataout_h"
type="conduit"
dir="end">
<port name="dataout_h" internal="dataout_h" />
</interface>
<interface
name="dataout_l"
internal="ip_arria10_ddio_in_1.dataout_l"
type="conduit"
dir="end">
<port name="dataout_l" internal="dataout_l" />
</interface>
<interface name="din" internal="ip_arria10_ddio_in_1.din" />
<interface name="dout" internal="ip_arria10_ddio_in_1.dout" />
<interface
name="pad_in"
internal="ip_arria10_ddio_in_1.pad_in"
type="conduit"
dir="end">
<port name="datain" internal="datain" />
</interface>
<interface name="pad_out" internal="ip_arria10_ddio_in_1.pad_out" />
<module
name="ip_arria10_ddio_in_1"
kind="altera_gpio"
version="19.3.0"
enabled="1"
autoexport="1">
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
<parameter name="EXT_DRIVER_PARAM" value="false" />
<parameter name="GENERATE_SDC_FILE" value="false" />
<parameter name="IP_MIGRATE_PORT_MAP_FILE">altddio_in_port_map.csv</parameter>
<parameter name="PIN_TYPE_GUI" value="Input" />
<parameter name="SIZE" value="1" />
<parameter name="SYS_INFO_DEVICE" value="10AX115U3F45E2SG" />
<parameter name="device_family" value="Arria 10" />
<parameter name="gui_areset_mode" value="Clear" />
<parameter name="gui_bus_hold" value="false" />
<parameter name="gui_diff_buff" value="false" />
<parameter name="gui_enable_cke" value="false" />
<parameter name="gui_enable_migratable_port_names" value="true" />
<parameter name="gui_enable_termination_ports" value="false" />
<parameter name="gui_hr_logic" value="false" />
<parameter name="gui_io_reg_mode" value="DDIO" />
<parameter name="gui_open_drain" value="false" />
<parameter name="gui_pseudo_diff" value="false" />
<parameter name="gui_separate_io_clks" value="false" />
<parameter name="gui_sreset_mode" value="None" />
<parameter name="gui_use_oe" value="false" />
</module>
</system>
libraries/technology/ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_out_1.ip 0 → 100644
+ 628
− 0
View file @ 12f3c29c
This diff is collapsed.
libraries/technology/ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_out_1.qsys deleted 100644 → 0
+ 0
− 110
View file @ 13fbc962
<?xml version="1.0" encoding="UTF-8"?>
<system name="ip_arria10_e2sg_ddio_out_1">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags="AUTHORSHIP=Intel Corporation"
categories="System"
tool="QsysStandard" />
<parameter name="bonusData"><![CDATA[bonusData
{
element $system
{
}
element ip_arria10_ddio_out_1
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
}
]]></parameter>
<parameter name="device" value="10AX115U3F45E2SG" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="2" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="false" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
<connPtSystemInfos/>
</systemInfosDefinition>]]></parameter>
<parameter name="systemScripts" value="" />
<parameter name="testBenchDutName" value="" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
name="aclr"
internal="ip_arria10_ddio_out_1.aclr"
type="conduit"
dir="end">
<port name="aclr" internal="aclr" />
</interface>
<interface
name="ck"
internal="ip_arria10_ddio_out_1.ck"
type="conduit"
dir="end">
<port name="outclock" internal="outclock" />
</interface>
<interface
name="datain_h"
internal="ip_arria10_ddio_out_1.datain_h"
type="conduit"
dir="end">
<port name="datain_h" internal="datain_h" />
</interface>
<interface
name="datain_l"
internal="ip_arria10_ddio_out_1.datain_l"
type="conduit"
dir="end">
<port name="datain_l" internal="datain_l" />
</interface>
<interface name="din" internal="ip_arria10_ddio_out_1.din" />
<interface
name="pad_out"
internal="ip_arria10_ddio_out_1.pad_out"
type="conduit"
dir="end">
<port name="dataout" internal="dataout" />
</interface>
<module
name="ip_arria10_ddio_out_1"
kind="altera_gpio"
version="19.3.0"
enabled="1"
autoexport="1">
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
<parameter name="EXT_DRIVER_PARAM" value="false" />
<parameter name="GENERATE_SDC_FILE" value="false" />
<parameter name="IP_MIGRATE_PORT_MAP_FILE">altddio_out_port_map.csv</parameter>
<parameter name="PIN_TYPE_GUI" value="Output" />
<parameter name="SIZE" value="1" />
<parameter name="SYS_INFO_DEVICE" value="10AX115U3F45E2SG" />
<parameter name="device_family" value="Arria 10" />
<parameter name="gui_areset_mode" value="Clear" />
<parameter name="gui_bus_hold" value="false" />
<parameter name="gui_diff_buff" value="false" />
<parameter name="gui_enable_cke" value="false" />
<parameter name="gui_enable_migratable_port_names" value="true" />
<parameter name="gui_enable_termination_ports" value="false" />
<parameter name="gui_hr_logic" value="false" />
<parameter name="gui_io_reg_mode" value="DDIO" />
<parameter name="gui_open_drain" value="false" />
<parameter name="gui_pseudo_diff" value="false" />
<parameter name="gui_separate_io_clks" value="false" />
<parameter name="gui_sreset_mode" value="None" />
<parameter name="gui_use_oe" value="false" />
</module>
</system>
libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/hdllib.cfg
+ 1
− 1
View file @ 12f3c29c
......@@ -21,5 +21,5 @@ quartus_qip_files =
[generate_ip_libs]
qsys-generate_ip_files =
ip_arria10_e2sg_ddr4_8g_1600.qsys
ip_arria10_e2sg_ddr4_8g_1600.ip
libraries/technology/ip_arria10_e2sg/ddr4_8g_2400/hdllib.cfg
+ 1
− 1
View file @ 12f3c29c
......@@ -20,5 +20,5 @@ quartus_qip_files =
[generate_ip_libs]
qsys-generate_ip_files =
ip_arria10_e2sg_ddr4_8g_2400.qsys
ip_arria10_e2sg_ddr4_8g_2400.ip
libraries/technology/ip_arria10_e2sg/fifo/hdllib.cfg
+ 3
− 3
View file @ 12f3c29c
......@@ -20,7 +20,7 @@ test_bench_files =
[generate_ip_libs]
qsys-generate_ip_files =
ip_arria10_e2sg_fifo_sc.qsys
ip_arria10_e2sg_fifo_dc.qsys
ip_arria10_e2sg_fifo_dc_mixed_widths.qsys
ip_arria10_e2sg_fifo_sc.ip
ip_arria10_e2sg_fifo_dc.ip
ip_arria10_e2sg_fifo_dc_mixed_widths.ip
libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_dc.ip 0 → 100644
+ 654
− 0
View file @ 12f3c29c
This diff is collapsed.
libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_dc.qsys deleted 100644 → 0
+ 0
− 116
View file @ 13fbc962
<?xml version="1.0" encoding="UTF-8"?>
<system name="ip_arria10_e2sg_fifo_dc">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags="AUTHORSHIP=Intel Corporation"
categories="System"
tool="QsysStandard" />
<parameter name="bonusData"><![CDATA[bonusData
{
element $system
{
}
element ip_arria10_fifo_dc
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
}
]]></parameter>
<parameter name="device" value="10AX115U3F45E2SG" />
<parameter name="deviceFamily" value="Arria 10" />
<parameter name="deviceSpeedGrade" value="2" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="false" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
<connPtSystemInfos/>
</systemInfosDefinition>]]></parameter>
<parameter name="systemScripts" value="" />
<parameter name="testBenchDutName" value="" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
name="fifo_input"
internal="ip_arria10_fifo_dc.fifo_input"
type="conduit"
dir="end">
<port name="aclr" internal="aclr" />
<port name="data" internal="data" />
<port name="rdclk" internal="rdclk" />
<port name="rdreq" internal="rdreq" />
<port name="wrclk" internal="wrclk" />
<port name="wrreq" internal="wrreq" />
</interface>
<interface
name="fifo_output"
internal="ip_arria10_fifo_dc.fifo_output"
type="conduit"
dir="end">
<port name="q" internal="q" />
<port name="rdempty" internal="rdempty" />
<port name="rdusedw" internal="rdusedw" />
<port name="wrfull" internal="wrfull" />
<port name="wrusedw" internal="wrusedw" />
</interface>
<module
name="ip_arria10_fifo_dc"
kind="fifo"
version="19.1"
enabled="1"
autoexport="1">
<parameter name="DEVICE_FAMILY" value="Arria 10" />
<parameter name="GUI_AlmostEmpty" value="false" />
<parameter name="GUI_AlmostEmptyThr" value="-1" />
<parameter name="GUI_AlmostFull" value="false" />
<parameter name="GUI_AlmostFullThr" value="-1" />
<parameter name="GUI_CLOCKS_ARE_SYNCHRONIZED" value="0" />
<parameter name="GUI_Clock" value="4" />
<parameter name="GUI_DISABLE_DCFIFO_EMBEDDED_TIMING_CONSTRAINT" value="true" />
<parameter name="GUI_Depth" value="256" />
<parameter name="GUI_ENABLE_ECC" value="false" />
<parameter name="GUI_Empty" value="true" />
<parameter name="GUI_Full" value="true" />
<parameter name="GUI_LE_BasedFIFO" value="false" />
<parameter name="GUI_LegacyRREQ" value="1" />
<parameter name="GUI_MAX_DEPTH" value="Auto" />
<parameter name="GUI_MAX_DEPTH_BY_9" value="false" />
<parameter name="GUI_OVERFLOW_CHECKING" value="false" />
<parameter name="GUI_Optimize" value="1" />
<parameter name="GUI_Optimize_max" value="1" />
<parameter name="GUI_RAM_BLOCK_TYPE" value="Auto" />
<parameter name="GUI_TESTBENCH" value="false" />
<parameter name="GUI_UNDERFLOW_CHECKING" value="false" />
<parameter name="GUI_UsedW" value="true" />
<parameter name="GUI_Width" value="8" />
<parameter name="GUI_dc_aclr" value="true" />
<parameter name="GUI_delaypipe" value="5" />
<parameter name="GUI_diff_widths" value="false" />
<parameter name="GUI_msb_usedw" value="false" />
<parameter name="GUI_output_width" value="8" />
<parameter name="GUI_read_aclr_synch" value="false" />
<parameter name="GUI_rsEmpty" value="true" />
<parameter name="GUI_rsFull" value="false" />
<parameter name="GUI_rsUsedW" value="true" />
<parameter name="GUI_sc_aclr" value="false" />
<parameter name="GUI_sc_sclr" value="false" />
<parameter name="GUI_synStage" value="3" />
<parameter name="GUI_write_aclr_synch" value="true" />
<parameter name="GUI_wsEmpty" value="false" />
<parameter name="GUI_wsFull" value="true" />
<parameter name="GUI_wsUsedW" value="true" />
</module>
</system>
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