Corrected typo in comment.

libraries/base/mm/src/vhdl/mm_latency_adapter.vhd

@@ -30,7 +30,7 @@
 --   When the in_mosi.waitrequest goes high, then this FIFO buffer can hold
 --   the in_mosi input that may still arrive, due to that the master at the
 --   input only notices the in_mosi.waitrequest from the output slave one
---   cylce later due to the pipelining.
+--   cycle later due to the pipelining.
 
 LIBRARY IEEE, common_lib;
 USE IEEE.STD_LOGIC_1164.ALL;