From 1051a243b4704531789518d90a61d5bb7b95b913 Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Tue, 10 Mar 2020 17:31:13 +0100
Subject: [PATCH] Corrected typo in comment.

---
 libraries/base/mm/src/vhdl/mm_latency_adapter.vhd | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/libraries/base/mm/src/vhdl/mm_latency_adapter.vhd b/libraries/base/mm/src/vhdl/mm_latency_adapter.vhd
index 4e7815df61..9ba97a6b80 100644
--- a/libraries/base/mm/src/vhdl/mm_latency_adapter.vhd
+++ b/libraries/base/mm/src/vhdl/mm_latency_adapter.vhd
@@ -30,7 +30,7 @@
 --   When the in_mosi.waitrequest goes high, then this FIFO buffer can hold
 --   the in_mosi input that may still arrive, due to that the master at the
 --   input only notices the in_mosi.waitrequest from the output slave one
---   cylce later due to the pipelining.
+--   cycle later due to the pipelining.
 
 LIBRARY IEEE, common_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
-- 
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