Prepare to clearly separate mm_bus combinatorial from pipelining.

libraries/base/mm/hdllib.cfg

@@ -13,8 +13,11 @@ synth_files =
     src/verilog/wbs_arbiter.v
     src/vhdl/mm_arbiter.vhd
     
-    src/vhdl/mm_slave_enable.vhd
+    src/vhdl/mm_pipeline.vhd
     src/vhdl/mm_latency_adapter.vhd
+    src/vhdl/mm_slave_enable.vhd
+    src/vhdl/mm_bus_comb.vhd
+    src/vhdl/mm_bus_pipe.vhd
     src/vhdl/mm_bus.vhd
     src/vhdl/mm_master_mux.vhd
     src/vhdl/mm_slave_mux.vhd