From 0b4439ff935cfc72e1b9670f9b8060a6a0605665 Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Thu, 14 Oct 2021 16:59:17 +0200
Subject: [PATCH] Initialize a_sint = 0 to avoid assert error at 0 ps.

---
 libraries/base/common/tb/vhdl/tb_common_to_sreal.vhd | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/libraries/base/common/tb/vhdl/tb_common_to_sreal.vhd b/libraries/base/common/tb/vhdl/tb_common_to_sreal.vhd
index 8cd012da5f..59377a5d8a 100644
--- a/libraries/base/common/tb/vhdl/tb_common_to_sreal.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_to_sreal.vhd
@@ -63,7 +63,7 @@ ARCHITECTURE tb OF tb_common_to_sreal IS
   SIGNAL rst              : STD_LOGIC := '1';
 
   SIGNAL a_real           : REAL := 0.0;
-  SIGNAL a_sint           : INTEGER;
+  SIGNAL a_sint           : INTEGER := 0;
   SIGNAL a_slv            : STD_LOGIC_VECTOR(c_width-1 DOWNTO 0) := (OTHERS => '0');
   SIGNAL dbg_resolution_w : INTEGER := 0;
   SIGNAL dbg_resolution   : REAL := 0.0;
-- 
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