diff --git a/libraries/base/common/tb/vhdl/tb_common_to_sreal.vhd b/libraries/base/common/tb/vhdl/tb_common_to_sreal.vhd
index 8cd012da5fd31e5886a77e4d6079e9de9ae1391c..59377a5d8a28fd3aff7e3149e82f12fc2e85fbd9 100644
--- a/libraries/base/common/tb/vhdl/tb_common_to_sreal.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_to_sreal.vhd
@@ -63,7 +63,7 @@ ARCHITECTURE tb OF tb_common_to_sreal IS
   SIGNAL rst              : STD_LOGIC := '1';
 
   SIGNAL a_real           : REAL := 0.0;
-  SIGNAL a_sint           : INTEGER;
+  SIGNAL a_sint           : INTEGER := 0;
   SIGNAL a_slv            : STD_LOGIC_VECTOR(c_width-1 DOWNTO 0) := (OTHERS => '0');
   SIGNAL dbg_resolution_w : INTEGER := 0;
   SIGNAL dbg_resolution   : REAL := 0.0;