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Commit 08506f4f authored by Pepping's avatar Pepping
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- Updated settings for requantizer. 

- Changed mmm and ctrl instances.
parent 2918b24b
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applications/apertif/designs/apertif_unb1_correlator/src/vhdl/apertif_unb1_correlator.vhd
+ 165
− 160
View file @ 08506f4f
......@@ -61,7 +61,7 @@ USE bf_lib.bf_pkg.ALL;
ENTITY apertif_unb1_correlator IS
GENERIC (
g_design_name : STRING := "apertif_unb1_correlator";
g_use_bg : BOOLEAN := FALSE; -- Overridden (TRUE) by TB but still a valid synthesis option; this replaces the 10GbE input stage with block gens.
g_use_bg : BOOLEAN := TRUE; -- Overridden (TRUE) by TB but still a valid synthesis option; this replaces the 10GbE input stage with block gens.
g_sim : BOOLEAN := FALSE; -- Overridden by TB
g_sim_fast : BOOLEAN := TRUE; -- TRUE = fast accumulator model and no inter-channel delay in the correlator output stream.
g_sim_unb_nr : NATURAL := 0;
......@@ -179,6 +179,7 @@ ARCHITECTURE str OF apertif_unb1_correlator IS
CONSTANT c_wpfb_nof_taps : NATURAL := 8; -- = 8 nof taps n the filter
CONSTANT c_wpfb_coef_w : NATURAL := 16; --FIXME: 9b does not work; needs updated coefficient files.
CONSTANT c_wpfb_in_dat_w : NATURAL := 8; --FIXME: should be 6b at some point
CONSTANT c_wpfb_out_dat_significant_w : NATURAL := sel_a_b(c_wpfb_in_dat_w = 6, 10, 12);
CONSTANT c_wpfb_out_dat_w : NATURAL := 16; --FIXME: Could be wider but is currently 9b to avoid the need for quantization: 9b -> mult -> 18b -> accu -> 32b at the corr output.
CONSTANT c_wpfb_use_separate : BOOLEAN := FALSE; -- = false for complex input, true for two real inputs
CONSTANT c_wpfb_use_reorder : BOOLEAN := FALSE;
......@@ -248,68 +249,77 @@ ARCHITECTURE str OF apertif_unb1_correlator IS
SIGNAL mm_clk : STD_LOGIC;
SIGNAL mm_locked : STD_LOGIC;
SIGNAL mm_rst : STD_LOGIC;
SIGNAL cal_clk : STD_LOGIC;
SIGNAL epcs_clk : STD_LOGIC;
SIGNAL dp_rst : STD_LOGIC;
SIGNAL dp_clk : STD_LOGIC;
SIGNAL dp_pps : STD_LOGIC;
SIGNAL sa_rst : STD_LOGIC;
SIGNAL eth1g_tse_clk : STD_LOGIC;
SIGNAL eth1g_mm_rst : STD_LOGIC;
SIGNAL eth1g_reg_interrupt : STD_LOGIC; -- Interrupt
-- PIOs
SIGNAL pout_wdi : STD_LOGIC;
-- MM WDI override
-- MM Register interfaces
SIGNAL reg_wdi_mosi : t_mem_mosi;
SIGNAL reg_wdi_miso : t_mem_miso;
-- MM PPSH
SIGNAL reg_ppsh_mosi : t_mem_mosi;
SIGNAL reg_ppsh_miso : t_mem_miso;
-- MM UniBoard system info
SIGNAL reg_unb_system_info_mosi : t_mem_mosi;
SIGNAL reg_unb_system_info_miso : t_mem_miso;
SIGNAL rom_unb_system_info_mosi : t_mem_mosi;
SIGNAL rom_unb_system_info_miso : t_mem_miso;
-- MM UniBoard I2C sens
SIGNAL reg_unb_sens_mosi : t_mem_mosi;
SIGNAL reg_unb_sens_miso : t_mem_miso;
-- MM eth1g
SIGNAL eth1g_tse_clk : STD_LOGIC;
SIGNAL eth1g_mm_rst : STD_LOGIC;
SIGNAL eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
SIGNAL eth1g_tse_miso : t_mem_miso;
SIGNAL eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
SIGNAL eth1g_reg_miso : t_mem_miso;
SIGNAL eth1g_reg_interrupt : STD_LOGIC; -- Interrupt
SIGNAL eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
SIGNAL reg_ppsh_mosi : t_mem_mosi;
SIGNAL reg_ppsh_miso : t_mem_miso;
SIGNAL eth1g_ram_mosi : t_mem_mosi;
SIGNAL eth1g_ram_miso : t_mem_miso;
-- Block generator
SIGNAL reg_diag_bg_mosi : t_mem_mosi;
SIGNAL reg_diag_bg_miso : t_mem_miso;
-- MM DP offload RX
SIGNAL eth1g_reg_mosi : t_mem_mosi;
SIGNAL eth1g_reg_miso : t_mem_miso;
SIGNAL eth1g_tse_mosi : t_mem_mosi;
SIGNAL eth1g_tse_miso : t_mem_miso;
SIGNAL reg_diag_bg_input_mosi : t_mem_mosi;
SIGNAL reg_diag_bg_input_miso : t_mem_miso;
SIGNAL reg_diag_bg_mesh_mosi : t_mem_mosi;
SIGNAL reg_diag_bg_mesh_miso : t_mem_miso;
SIGNAL ram_diag_bg_mesh_mosi : t_mem_mosi;
SIGNAL ram_diag_bg_mesh_miso : t_mem_miso;
SIGNAL reg_diagnostics_mosi : t_mem_mosi;
SIGNAL reg_diagnostics_miso : t_mem_miso;
SIGNAL reg_tr_nonbonded_mosi : t_mem_mosi;
SIGNAL reg_tr_nonbonded_miso : t_mem_miso;
SIGNAL reg_diag_data_buf_input_mosi : t_mem_mosi;
SIGNAL reg_diag_data_buf_input_miso : t_mem_miso;
SIGNAL ram_diag_data_buf_input_mosi : t_mem_mosi;
SIGNAL ram_diag_data_buf_input_miso : t_mem_miso;
SIGNAL reg_diag_data_buf_mesh_mosi : t_mem_mosi;
SIGNAL reg_diag_data_buf_mesh_miso : t_mem_miso;
SIGNAL ram_diag_data_buf_mesh_mosi : t_mem_mosi;
SIGNAL ram_diag_data_buf_mesh_miso : t_mem_miso;
SIGNAL ram_fil_coefs_mosi : t_mem_mosi;
SIGNAL ram_fil_coefs_miso : t_mem_miso;
SIGNAL reg_mdio_0_mosi : t_mem_mosi;
SIGNAL reg_mdio_0_miso : t_mem_miso;
SIGNAL reg_mdio_1_mosi : t_mem_mosi;
SIGNAL reg_mdio_1_miso : t_mem_miso;
SIGNAL reg_mdio_2_mosi : t_mem_mosi;
SIGNAL reg_mdio_2_miso : t_mem_miso;
SIGNAL reg_dp_offload_rx_hdr_dat_mosi : t_mem_mosi;
SIGNAL reg_dp_offload_rx_hdr_dat_miso : t_mem_miso;
-- BSN monitors
SIGNAL reg_dp_offload_tx_hdr_dat_mosi : t_mem_mosi;
SIGNAL reg_dp_offload_tx_hdr_dat_miso : t_mem_miso;
SIGNAL reg_tr_10gbe_mosi : t_mem_mosi;
SIGNAL reg_tr_10gbe_miso : t_mem_miso;
SIGNAL reg_tr_xaui_mosi : t_mem_mosi;
SIGNAL reg_tr_xaui_miso : t_mem_miso;
SIGNAL reg_bsn_monitor_mosi : t_mem_mosi;
SIGNAL reg_bsn_monitor_miso : t_mem_miso;
-- MM Filterbank
SIGNAL ram_fil_coefs_mosi : t_mem_mosi;
SIGNAL ram_fil_coefs_miso : t_mem_miso;
-- MM Databuffer
SIGNAL ram_diag_data_buf_mosi : t_mem_mosi;
SIGNAL ram_diag_data_buf_miso : t_mem_miso;
SIGNAL reg_diag_data_buf_mosi : t_mem_mosi;
SIGNAL reg_diag_data_buf_miso : t_mem_miso;
-- MM 1GbE visibility offload TX
SIGNAL reg_dp_offload_tx_hdr_dat_mosi : t_mem_mosi;
SIGNAL reg_dp_offload_tx_hdr_dat_miso : t_mem_miso;
SIGNAL reg_mdio_mosi_arr : t_mem_mosi_arr(c_unb1_board_nof_mdio-1 DOWNTO 0);
SIGNAL reg_mdio_miso_arr : t_mem_miso_arr(c_unb1_board_nof_mdio-1 DOWNTO 0);
-- Interface: 10GbE
SIGNAL xaui_tx_arr : t_xaui_arr(c_nof_10GbE_streams-1 DOWNTO 0);
......@@ -319,12 +329,6 @@ ARCHITECTURE str OF apertif_unb1_correlator IS
SIGNAL mdio_mdc_arr : STD_LOGIC_VECTOR(c_nof_10GbE_streams-1 DOWNTO 0);
SIGNAL mdio_mdat_in_arr : STD_LOGIC_VECTOR(c_nof_10GbE_streams-1 DOWNTO 0);
SIGNAL mdio_mdat_oen_arr : STD_LOGIC_VECTOR(c_nof_10GbE_streams-1 DOWNTO 0);
SIGNAL reg_tr_10GbE_mosi : t_mem_mosi;
SIGNAL reg_tr_10GbE_miso : t_mem_miso;
SIGNAL reg_tr_xaui_mosi : t_mem_mosi;
SIGNAL reg_tr_xaui_miso : t_mem_miso;
SIGNAL reg_mdio_mosi_arr : t_mem_mosi_arr(c_unb1_board_nof_mdio-1 DOWNTO 0);
SIGNAL reg_mdio_miso_arr : t_mem_miso_arr(c_unb1_board_nof_mdio-1 DOWNTO 0);
-- DP offload RX
SIGNAL dp_offload_rx_snk_in_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0);
......@@ -406,8 +410,8 @@ BEGIN
dp_rst => dp_rst,
dp_clk => dp_clk,
reg_bg_ctrl_mosi => reg_diag_bg_mosi,
reg_bg_ctrl_miso => reg_diag_bg_miso,
reg_bg_ctrl_mosi => reg_diag_bg_input_mosi,
reg_bg_ctrl_miso => reg_diag_bg_input_miso,
out_sosi_arr => interleaved_arr
);
......@@ -690,10 +694,10 @@ BEGIN
dp_rst => dp_rst,
dp_clk => dp_clk,
ram_data_buf_mosi => ram_diag_data_buf_mosi,
ram_data_buf_miso => ram_diag_data_buf_miso,
reg_data_buf_mosi => reg_diag_data_buf_mosi, --FIXME address space is wrong (1 bit)
reg_data_buf_miso => reg_diag_data_buf_miso,
ram_data_buf_mosi => ram_diag_data_buf_input_mosi,
ram_data_buf_miso => ram_diag_data_buf_input_miso,
reg_data_buf_mosi => reg_diag_data_buf_input_mosi, --FIXME address space is wrong (1 bit)
reg_data_buf_miso => reg_diag_data_buf_input_miso,
in_sync => diag_data_buf_snk_in_arr(0).sync,
in_sosi_arr => diag_data_buf_snk_in_arr
......@@ -1025,7 +1029,7 @@ BEGIN
GENERIC MAP (
g_complex => TRUE,
g_representation => "SIGNED",
g_lsb_w => c_wpfb_out_dat_w-c_cor_in_dat_w,
g_lsb_w => c_wpfb_out_dat_significant_w-c_cor_in_dat_w,
g_lsb_round => FALSE,
g_lsb_round_clip => FALSE,
g_msb_clip => FALSE,
......@@ -1187,27 +1191,34 @@ BEGIN
g_udp_offload_nof_streams => 1,
g_use_phy => c_use_phy,
g_aux => c_unb1_board_aux,
g_dp_clk_use_pll => TRUE
g_dp_clk_use_pll => TRUE,
g_xo_clk_use_pll => TRUE
)
PORT MAP (
-- Clock an reset signals
-- Clock and reset signals
cs_sim => cs_sim,
xo_clk => xo_clk,
xo_rst => xo_rst,
xo_rst_n => xo_rst_n,
mm_clk_out => mm_clk,
mm_clk => mm_clk,
mm_locked => mm_locked,
mm_rst => mm_rst,
epcs_clk => '0',
mm_locked => mm_locked,
mm_locked_out => mm_locked,
epcs_clk => epcs_clk,
epcs_clk_out => epcs_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
dp_pps => OPEN,
dp_pps => dp_pps,
dp_rst_in => dp_rst,
dp_clk_in => dp_clk,
cal_rec_clk => cal_clk,
-- Toggle WDI
pout_wdi => pout_wdi,
......@@ -1231,7 +1242,8 @@ BEGIN
reg_ppsh_miso => reg_ppsh_miso,
-- eth1g
eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
eth1g_tse_clk_out => eth1g_tse_clk,
eth1g_tse_clk => eth1g_tse_clk,
eth1g_mm_rst => eth1g_mm_rst,
eth1g_tse_mosi => eth1g_tse_mosi,
eth1g_tse_miso => eth1g_tse_miso,
......@@ -1240,6 +1252,7 @@ BEGIN
eth1g_reg_interrupt => eth1g_reg_interrupt,
eth1g_ram_mosi => eth1g_ram_mosi,
eth1g_ram_miso => eth1g_ram_miso,
-- eth1g UDP streaming ports
udp_tx_sosi_arr => dp_offload_tx_src_out_arr,
udp_tx_siso_arr => dp_offload_tx_src_in_arr,
......@@ -1267,88 +1280,80 @@ BEGIN
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
u_mmm : ENTITY work.mmm_apertif_unb1_correlator
u_mmm_apertif_unb1_correlator : ENTITY work.mmm_apertif_unb1_correlator
GENERIC MAP(
g_sim => g_sim,
g_sim_unb_nr => g_sim_unb_nr,
g_sim_node_nr => g_sim_node_nr,
g_wpfb => c_wpfb,
g_hdr_field_arr => c_apertif_udp_offload_hdr_field_arr
g_sim_node_nr => g_sim_node_nr
)
PORT MAP(
xo_clk => xo_clk,
xo_rst_n => xo_rst_n,
xo_rst => xo_rst,
mm_rst => mm_rst,
mm_clk => mm_clk,
mm_locked => mm_locked,
-- PIOs
mm_rst => mm_rst,
pout_wdi => pout_wdi,
-- Manual WDI override
reg_wdi_mosi => reg_wdi_mosi,
reg_wdi_miso => reg_wdi_miso,
-- system_info
reg_unb_system_info_mosi => reg_unb_system_info_mosi,
reg_unb_system_info_miso => reg_unb_system_info_miso,
rom_unb_system_info_mosi => rom_unb_system_info_mosi,
rom_unb_system_info_miso => rom_unb_system_info_miso,
-- UniBoard I2C sensors
reg_unb_sens_mosi => reg_unb_sens_mosi,
reg_unb_sens_miso => reg_unb_sens_miso,
-- PPSH
reg_ppsh_mosi => reg_ppsh_mosi,
reg_ppsh_miso => reg_ppsh_miso,
-- Block generator
reg_diag_bg_mosi => reg_diag_bg_mosi,
reg_diag_bg_miso => reg_diag_bg_miso,
-- 10 GbE
reg_tr_10GbE_mosi => reg_tr_10GbE_mosi,
reg_tr_10GbE_miso => reg_tr_10GbE_miso,
reg_tr_xaui_mosi => reg_tr_xaui_mosi,
reg_tr_xaui_miso => reg_tr_xaui_miso,
reg_mdio_mosi_arr => reg_mdio_mosi_arr,
reg_mdio_miso_arr => reg_mdio_miso_arr,
-- DP offload RX
eth1g_mm_rst => eth1g_mm_rst,
eth1g_reg_interrupt => eth1g_reg_interrupt,
eth1g_ram_mosi => eth1g_ram_mosi,
eth1g_ram_miso => eth1g_ram_miso,
eth1g_reg_mosi => eth1g_reg_mosi,
eth1g_reg_miso => eth1g_reg_miso,
eth1g_tse_mosi => eth1g_tse_mosi,
eth1g_tse_miso => eth1g_tse_miso,
reg_diag_bg_input_mosi => reg_diag_bg_input_mosi,
reg_diag_bg_input_miso => reg_diag_bg_input_miso,
reg_diag_bg_mesh_mosi => reg_diag_bg_mesh_mosi,
reg_diag_bg_mesh_miso => reg_diag_bg_mesh_miso,
ram_diag_bg_mesh_mosi => ram_diag_bg_mesh_mosi,
ram_diag_bg_mesh_miso => ram_diag_bg_mesh_miso,
reg_diagnostics_mosi => reg_diagnostics_mosi,
reg_diagnostics_miso => reg_diagnostics_miso,
reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
reg_diag_data_buf_input_mosi => reg_diag_data_buf_input_mosi,
reg_diag_data_buf_input_miso => reg_diag_data_buf_input_miso,
ram_diag_data_buf_input_mosi => ram_diag_data_buf_input_mosi,
ram_diag_data_buf_input_miso => ram_diag_data_buf_input_miso,
reg_diag_data_buf_mesh_mosi => reg_diag_data_buf_mesh_mosi,
reg_diag_data_buf_mesh_miso => reg_diag_data_buf_mesh_miso,
ram_diag_data_buf_mesh_mosi => ram_diag_data_buf_mesh_mosi,
ram_diag_data_buf_mesh_miso => ram_diag_data_buf_mesh_miso,
ram_fil_coefs_mosi => ram_fil_coefs_mosi,
ram_fil_coefs_miso => ram_fil_coefs_miso,
reg_mdio_0_mosi => reg_mdio_0_mosi,
reg_mdio_0_miso => reg_mdio_0_miso,
reg_mdio_1_mosi => reg_mdio_1_mosi,
reg_mdio_1_miso => reg_mdio_1_miso,
reg_mdio_2_mosi => reg_mdio_2_mosi,
reg_mdio_2_miso => reg_mdio_2_miso,
reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
reg_bsn_monitor_miso => reg_bsn_monitor_miso,
-- . Data buffers
reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
reg_diag_data_buf_miso => reg_diag_data_buf_miso,
ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
ram_diag_data_buf_miso => ram_diag_data_buf_miso,
-- 1GbE visibility offload TX
reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
reg_tr_10gbe_mosi => reg_tr_10gbe_mosi,
reg_tr_10gbe_miso => reg_tr_10gbe_miso,
reg_tr_xaui_mosi => reg_tr_xaui_mosi,
reg_tr_xaui_miso => reg_tr_xaui_miso,
reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
reg_bsn_monitor_miso => reg_bsn_monitor_miso
);
-- Filter coefficients
ram_fil_coefs_mosi => ram_fil_coefs_mosi,
ram_fil_coefs_miso => ram_fil_coefs_miso,
-- eth1g
eth1g_tse_clk => eth1g_tse_clk,
eth1g_mm_rst => eth1g_mm_rst,
eth1g_tse_mosi => eth1g_tse_mosi,
eth1g_tse_miso => eth1g_tse_miso,
eth1g_reg_mosi => eth1g_reg_mosi,
eth1g_reg_miso => eth1g_reg_miso,
eth1g_reg_interrupt => eth1g_reg_interrupt,
eth1g_ram_mosi => eth1g_ram_mosi,
eth1g_ram_miso => eth1g_ram_miso
);
reg_mdio_mosi_arr(0) <= reg_mdio_0_mosi;
reg_mdio_mosi_arr(1) <= reg_mdio_1_mosi;
reg_mdio_mosi_arr(2) <= reg_mdio_2_mosi;
reg_mdio_0_miso <= reg_mdio_miso_arr(0);
reg_mdio_1_miso <= reg_mdio_miso_arr(1);
reg_mdio_2_miso <= reg_mdio_miso_arr(2);
END str;
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