Delete

applications/apertif/designs/apertif_unb1_correlator/revisions/apertif_unb1_correlator_full/tb_apertif_unb1_correlator_full.vhd.bak

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---
--- Copyright (C) 2014
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
--- Purpose:
--- Description:
--- Usage:
-
-LIBRARY IEEE, common_lib, unb1_board_lib, i2c_lib;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.ALL;
-USE common_lib.common_pkg.ALL;
-USE unb1_board_lib.unb1_board_pkg.ALL;
-USE common_lib.tb_common_pkg.ALL;
-
-ENTITY tb_apertif_unb1_correlator_full IS
-END tb_apertif_unb1_correlator_full;
-
-ARCHITECTURE tb OF tb_apertif_unb1_correlator_full IS
-
-  CONSTANT c_sim             : BOOLEAN := TRUE;
-
-  CONSTANT c_unb_nr          : NATURAL := 0; -- UniBoard 0
-  CONSTANT c_node_nr         : NATURAL := 7; -- Back node 3
-  CONSTANT c_id              : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb_nr, c_unb1_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb1_board_nof_chip_w);
-
-  CONSTANT c_version         : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
-  CONSTANT c_fw_version      : t_unb1_board_fw_version := (1, 0);
-
-  CONSTANT c_cable_delay     : TIME := 12 ns;
-  CONSTANT c_eth_clk_period  : TIME := 40 ns;  -- 25 MHz XO on UniBoard
-  CONSTANT c_sa_clk_period   : TIME := 6.4 ns;  
-  CONSTANT c_clk_period      : TIME := 5 ns; 
-  CONSTANT c_pps_period      : NATURAL := 1000; 
-
-
-  -- DUT
-  SIGNAL clk                 : STD_LOGIC := '0';
-  SIGNAL pps                 : STD_LOGIC := '0';
-  SIGNAL pps_rst             : STD_LOGIC := '0';
-  SIGNAL sa_clk              : STD_LOGIC := '1';
-
-  SIGNAL WDI                 : STD_LOGIC;
-  SIGNAL INTA                : STD_LOGIC;
-  SIGNAL INTB                : STD_LOGIC;
-
-  SIGNAL eth_clk             : STD_LOGIC := '0';
-  SIGNAL eth_txp             : STD_LOGIC;
-  SIGNAL eth_rxp             : STD_LOGIC;
-  
-  SIGNAL VERSION             : STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0) := c_version; 
-  SIGNAL ID                  : STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0)      := c_id;
-  SIGNAL TESTIO              : STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
-
-  SIGNAL sens_scl            : STD_LOGIC;
-  SIGNAL sens_sda            : STD_LOGIC;
-  SIGNAL si_fn_0_tx          : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS => '0');  
- 
-  SIGNAL fn_bn_0_tx          : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
-  SIGNAL fn_bn_1_tx          : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
-  SIGNAL fn_bn_2_tx          : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
-  SIGNAL fn_bn_3_tx          : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
-
-BEGIN
-
-  ----------------------------------------------------------------------------
-  -- System setup
-  ----------------------------------------------------------------------------
-  clk     <= NOT clk AFTER c_clk_period/2;        -- External clock (200 MHz)
-  eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2;  -- Ethernet ref clock (25 MHz)
-  sa_clk  <= NOT sa_clk  AFTER c_sa_clk_period/2;
-  
-  INTA <= 'H';  -- pull up
-  INTB <= 'H';  -- pull up
-
-  sens_scl <= 'H';  -- pull up
-  sens_sda <= 'H';  -- pull up
-
-  ------------------------------------------------------------------------------
-  -- External PPS
-  ------------------------------------------------------------------------------  
-  proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, clk, pps);
-  
-  ------------------------------------------------------------------------------
-  -- DUT
-  ------------------------------------------------------------------------------
-  u_dut : ENTITY work.apertif_unb1_correlator_full
-    GENERIC MAP (
-      g_sim         => c_sim,
-      g_sim_unb_nr  => c_unb_nr,
-      g_sim_node_nr => c_node_nr
-    )
-    PORT MAP (
-      -- GENERAL
-      CLK         => clk,
-      PPS         => pps,
-      WDI         => WDI,
-      INTA        => INTA,
-      INTB        => INTB,
-
-      sens_sc     => sens_scl,
-      sens_sd     => sens_sda,
-
-      -- Others
-      VERSION     => VERSION,
-      ID          => ID,
-      TESTIO      => TESTIO,
-
-      -- 1GbE Control Interface
-      ETH_clk     => eth_clk,
-      ETH_SGIN    => eth_rxp,
-      ETH_SGOUT   => eth_txp,
-      
-      -- Transceiver clocks
-      SA_CLK      => sa_clk,  --  : IN  STD_LOGIC; -- SerDes Clock BN-BI / SI_FN
-      SB_CLK      => sa_clk,
-
-      -- Serial I/O
-      SI_FN_0_RX  => si_fn_0_tx,
-      SI_FN_1_RX  => si_fn_0_tx,
-      SI_FN_2_RX  => si_fn_0_tx,
-      SI_FN_3_RX  => si_fn_0_tx,
-
-      FN_BN_0_RX  => fn_bn_0_tx,
-      FN_BN_0_TX  => fn_bn_0_tx,
-
-      FN_BN_1_RX  => fn_bn_1_tx,
-      FN_BN_1_tX  => fn_bn_1_tx,
-
-      FN_BN_2_RX  => fn_bn_2_tx,
-      FN_BN_2_TX  => fn_bn_2_tx,
-
-      FN_BN_3_RX  => fn_bn_3_tx, 
-      FN_BN_3_TX  => fn_bn_3_tx  
-    );
-
-END tb;