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-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- Purpose: IP components declarations for various devices that get wrapped by the tech components
LIBRARY IEEE, technology_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE technology_lib.technology_pkg.ALL;
PACKAGE tech_10gbase_r_component_pkg IS
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CONSTANT tech_10gbase_r_ref_clk_period : TIME := 1551520 fs; -- = 1.551520 ns ~= 644.53125 MHz
CONSTANT tech_10gbase_r_clk_156_period : TIME := (tech_10gbase_r_ref_clk_period*33)/8; -- = 6.400020 ns ~= 156.25 MHz
CONSTANT tech_10gbase_r_clk_312_period : TIME := (tech_10gbase_r_ref_clk_period*33)/16; -- = 3.200010 ns ~= 312.5 MHz
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------------------------------------------------------------------------------
-- ip_arria10
------------------------------------------------------------------------------
-- Copied from entity $RADIOHDL/libraries/technology/ip_arria10/phy_10gbase_r/ip_arria10_phy_10gbase_r_top.vhd
COMPONENT ip_arria10_phy_10gbase_r_top IS
PORT (
tx_analogreset : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
tx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
rx_analogreset : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
rx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
tx_cal_busy : out std_logic_vector(0 downto 0); -- tx_cal_busy.tx_cal_busy
rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy.rx_cal_busy
tx_serial_clk0 : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_serial_clk0.clk
rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk
tx_serial_data : out std_logic_vector(0 downto 0); -- tx_serial_data.tx_serial_data
rx_serial_data : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
rx_is_lockedtoref : out std_logic_vector(0 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
rx_is_lockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
tx_coreclkin : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_coreclkin.clk
rx_coreclkin : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_coreclkin.clk
tx_clkout : out std_logic_vector(0 downto 0); -- tx_clkout.clk
rx_clkout : out std_logic_vector(0 downto 0); -- rx_clkout.clk
tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
rx_parallel_data : out std_logic_vector(63 downto 0); -- rx_parallel_data.rx_parallel_data
tx_pma_div_clkout : out std_logic_vector(0 downto 0); -- tx_pma_div_clkout.clk
tx_control : in std_logic_vector(7 downto 0) := (others => '0'); -- tx_control.tx_control
tx_err_ins : in std_logic := '0'; -- tx_err_ins.tx_err_ins
unused_tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0'); -- unused_tx_parallel_data.unused_tx_parallel_data
unused_tx_control : in std_logic_vector(8 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
rx_control : out std_logic_vector(7 downto 0); -- rx_control.rx_control
unused_rx_parallel_data : out std_logic_vector(63 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
unused_rx_control : out std_logic_vector(11 downto 0); -- unused_rx_control.unused_rx_control
tx_enh_data_valid : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
tx_enh_fifo_full : out std_logic_vector(0 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
tx_enh_fifo_pfull : out std_logic_vector(0 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
tx_enh_fifo_empty : out std_logic_vector(0 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
tx_enh_fifo_pempty : out std_logic_vector(0 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
rx_enh_data_valid : out std_logic_vector(0 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
rx_enh_fifo_full : out std_logic_vector(0 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
rx_enh_fifo_empty : out std_logic_vector(0 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
rx_enh_fifo_del : out std_logic_vector(0 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
rx_enh_fifo_insert : out std_logic_vector(0 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
rx_enh_highber : out std_logic_vector(0 downto 0); -- rx_enh_highber.rx_enh_highber
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rx_enh_blk_lock : out std_logic_vector(0 downto 0) -- rx_enh_blk_lock.rx_enh_blk_lock
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);
END COMPONENT;
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-- Copied from entity $RADIOHDL/libraries/technology/ip_arria10/transceiver_pll_156_312/ip_arria10_transceiver_pll_156_312_top.vhd
COMPONENT ip_arria10_transceiver_pll_156_312_top IS
PORT (
pll_refclk0 : in std_logic := '0'; -- pll_refclk0.clk
pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown
pll_locked : out std_logic; -- pll_locked.pll_locked
outclk0 : out std_logic; -- outclk0.clk
pll_cal_busy : out std_logic; -- pll_cal_busy.pll_cal_busy
outclk1 : out std_logic -- outclk1.clk
);
END COMPONENT;
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-- Copied from entity $RADIOHDL/libraries/technology/ip_arria10/transceiver_pll_10g/ip_arria10_transceiver_pll_10g_top.vhd
COMPONENT ip_arria10_transceiver_pll_10g_top IS
PORT (
pll_powerdown : in std_logic := '0'; -- pll_powerdown.pll_powerdown
pll_refclk0 : in std_logic := '0'; -- pll_refclk0.clk
tx_serial_clk : out std_logic; -- tx_serial_clk.clk
pll_locked : out std_logic; -- pll_locked.pll_locked
pll_cal_busy : out std_logic -- pll_cal_busy.pll_cal_busy
);
END COMPONENT;
-- Copied from entity $RADIOHDL/libraries/technology/ip_arria10/transceiver_reset_controller_1/ip_arria10_transceiver_reset_controller_1_top.vhd
COMPONENT ip_arria10_transceiver_reset_controller_1_top IS
PORT (
clock : in std_logic := '0'; -- clock.clk
reset : in std_logic := '0'; -- reset.reset
pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown.pll_powerdown
tx_analogreset : out std_logic_vector(0 downto 0); -- tx_analogreset.tx_analogreset
tx_digitalreset : out std_logic_vector(0 downto 0); -- tx_digitalreset.tx_digitalreset
tx_ready : out std_logic_vector(0 downto 0); -- tx_ready.tx_ready
pll_locked : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_locked.pll_locked
pll_select : in std_logic_vector(0 downto 0) := (others => '0'); -- pll_select.pll_select
tx_cal_busy : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_cal_busy.tx_cal_busy
rx_analogreset : out std_logic_vector(0 downto 0); -- rx_analogreset.rx_analogreset
rx_digitalreset : out std_logic_vector(0 downto 0); -- rx_digitalreset.rx_digitalreset
rx_ready : out std_logic_vector(0 downto 0); -- rx_ready.rx_ready
rx_is_lockedtodata : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_is_lockedtodata.rx_is_lockedtodata
rx_cal_busy : in std_logic_vector(0 downto 0) := (others => '0') -- rx_cal_busy.rx_cal_busy
);
END COMPONENT;
END tech_10gbase_r_component_pkg;