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Commit ec520b41 authored by Stefano Di Frischia's avatar Stefano Di Frischia
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Merge branch 'master' into L2SS-643-calculate-beamlet-bfweights

parents 50b8b688 bc0a21ee
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1 merge request!294Resolve L2SS-643 "Calculate beamlet bfweights"
...@@ -165,9 +165,8 @@ class SDP(opcua_device): ...@@ -165,9 +165,8 @@ class SDP(opcua_device):
FPGA_jesd204b_rx_err1_R = attribute_wrapper(comms_annotation=["FPGA_jesd204b_rx_err1_R"], datatype=numpy.uint32, dims=(S_pn, N_pn)) FPGA_jesd204b_rx_err1_R = attribute_wrapper(comms_annotation=["FPGA_jesd204b_rx_err1_R"], datatype=numpy.uint32, dims=(S_pn, N_pn))
FPGA_signal_input_bsn_R = attribute_wrapper(comms_annotation=["FPGA_signal_input_bsn_R"], datatype=numpy.int64, dims=(N_pn,)) FPGA_signal_input_bsn_R = attribute_wrapper(comms_annotation=["FPGA_signal_input_bsn_R"], datatype=numpy.int64, dims=(N_pn,))
FPGA_signal_input_nof_blocks_R = attribute_wrapper(comms_annotation=["FPGA_signal_input_nof_blocks_R"], datatype=numpy.int32, dims=(N_pn,)) FPGA_signal_input_nof_packets_R = attribute_wrapper(comms_annotation=["FPGA_signal_input_nof_packets_R"], datatype=numpy.int32, dims=(N_pn,))
FPGA_signal_input_nof_samples_R = attribute_wrapper(comms_annotation=["FPGA_signal_input_nof_samples_R"], datatype=numpy.int32, dims=(N_pn,)) FPGA_signal_input_nof_samples_R = attribute_wrapper(comms_annotation=["FPGA_signal_input_nof_samples_R"], datatype=numpy.int32, dims=(N_pn,))
FPGA_signal_input_nof_err_R = attribute_wrapper(comms_annotation=["FPGA_signal_input_nof_err_R"], datatype=numpy.int32, dims=(N_pn,))
FPGA_signal_input_samples_delay_R = attribute_wrapper(comms_annotation=["FPGA_signal_input_samples_delay_R"], datatype=numpy.uint32, dims=(S_pn, N_pn)) FPGA_signal_input_samples_delay_R = attribute_wrapper(comms_annotation=["FPGA_signal_input_samples_delay_R"], datatype=numpy.uint32, dims=(S_pn, N_pn))
FPGA_signal_input_samples_delay_RW = attribute_wrapper(comms_annotation=["FPGA_signal_input_samples_delay_RW"], datatype=numpy.uint32, dims=(S_pn, N_pn), access=AttrWriteType.READ_WRITE) FPGA_signal_input_samples_delay_RW = attribute_wrapper(comms_annotation=["FPGA_signal_input_samples_delay_RW"], datatype=numpy.uint32, dims=(S_pn, N_pn), access=AttrWriteType.READ_WRITE)
......
...@@ -13,6 +13,7 @@ from tangostationcontrol.integration_test.device_proxy import TestDeviceProxy ...@@ -13,6 +13,7 @@ from tangostationcontrol.integration_test.device_proxy import TestDeviceProxy
from tangostationcontrol.integration_test import base from tangostationcontrol.integration_test import base
class TestProxyAttributeAccess(base.IntegrationTestCase): class TestProxyAttributeAccess(base.IntegrationTestCase):
""" Test whether DeviceProxy's can always access attributes immediately after turning them on. """ """ Test whether DeviceProxy's can always access attributes immediately after turning them on. """
......
...@@ -16,6 +16,7 @@ from tangostationcontrol.integration_test.device_proxy import TestDeviceProxy ...@@ -16,6 +16,7 @@ from tangostationcontrol.integration_test.device_proxy import TestDeviceProxy
import time import time
from datetime import datetime from datetime import datetime
class TestArchiver(BaseIntegrationTestCase): class TestArchiver(BaseIntegrationTestCase):
def setUp(self): def setUp(self):
......
...@@ -14,6 +14,7 @@ from tango import DevState ...@@ -14,6 +14,7 @@ from tango import DevState
import json import json
import pkg_resources import pkg_resources
class TestArchiverUtil(BaseIntegrationTestCase): class TestArchiverUtil(BaseIntegrationTestCase):
def setUp(self): def setUp(self):
......
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