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Commit 8ba94956 authored by Stefano Di Frischia's avatar Stefano Di Frischia
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Merge branch 'L2SS-1008-beamlet-source-addresses' into 'master' 

Resolve L2SS-1008 "Beamlet source addresses"

Closes L2SS-1008

See merge request !460
parents 6870bb0a 45983926
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1 merge request!460Resolve L2SS-1008 "Beamlet source addresses"
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CDB/stations/CS001_ConfigDb.json
+ 54
− 0
View file @ 8ba94956
...@@ -126,6 +126,60 @@ ...@@ -126,6 +126,60 @@
"OPC_Time_Out": [ "OPC_Time_Out": [
"5.0" "5.0"
], ],
"FPGA_beamlet_output_hdr_eth_source_mac_RW_default": [
"00:22:86:00:01:00",
"00:22:86:00:01:01",
"00:22:86:00:01:02",
"00:22:86:00:01:03",
"00:22:86:00:01:04",
"00:22:86:00:01:05",
"00:22:86:00:01:06",
"00:22:86:00:01:07",
"00:22:86:00:01:08",
"00:22:86:00:01:09",
"00:22:86:00:01:10",
"00:22:86:00:01:11",
"00:22:86:00:01:12",
"00:22:86:00:01:13",
"00:22:86:00:01:14",
"00:22:86:00:01:15"
],
"FPGA_beamlet_output_hdr_ip_source_address_RW_default": [
"10.175.1.0",
"10.175.1.1",
"10.175.1.2",
"10.175.1.3",
"10.175.1.4",
"10.175.1.5",
"10.175.1.6",
"10.175.1.7",
"10.175.1.8",
"10.175.1.9",
"10.175.1.10",
"10.175.1.11",
"10.175.1.12",
"10.175.1.13",
"10.175.1.14",
"10.175.1.15"
],
"FPGA_beamlet_output_hdr_udp_source_port_RW_default": [
"4346",
"4347",
"4348",
"4349",
"4350",
"4351",
"4352",
"4353",
"4354",
"4355",
"4356",
"4357",
"4358",
"4359",
"4360",
"4361"
],
"FPGA_beamlet_output_hdr_eth_destination_mac_RW_default": [ "FPGA_beamlet_output_hdr_eth_destination_mac_RW_default": [
"3c:ec:ef:86:2f:b7", "3c:ec:ef:86:2f:b7",
"3c:ec:ef:86:2f:b7", "3c:ec:ef:86:2f:b7",
......
CDB/stations/simulators_ConfigDb.json
+ 54
− 0
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...@@ -84,6 +84,60 @@ ...@@ -84,6 +84,60 @@
"OPC_Time_Out": [ "OPC_Time_Out": [
"5.0" "5.0"
], ],
"FPGA_beamlet_output_hdr_eth_source_mac_RW_default": [
"00:11:22:33:44:00",
"00:11:22:33:44:01",
"00:11:22:33:44:02",
"00:11:22:33:44:03",
"00:11:22:33:44:04",
"00:11:22:33:44:05",
"00:11:22:33:44:06",
"00:11:22:33:44:07",
"00:11:22:33:44:08",
"00:11:22:33:44:09",
"00:11:22:33:44:10",
"00:11:22:33:44:11",
"00:11:22:33:44:12",
"00:11:22:33:44:13",
"00:11:22:33:44:14",
"00:11:22:33:44:15"
],
"FPGA_beamlet_output_hdr_ip_source_address_RW_default": [
"10.0.0.0",
"10.0.0.1",
"10.0.0.2",
"10.0.0.3",
"10.0.0.4",
"10.0.0.5",
"10.0.0.6",
"10.0.0.7",
"10.0.0.8",
"10.0.0.9",
"10.0.0.10",
"10.0.0.11",
"10.0.0.12",
"10.0.0.13",
"10.0.0.14",
"10.0.0.15"
],
"FPGA_beamlet_output_hdr_udp_source_port_RW_default": [
"4346",
"4347",
"4348",
"4349",
"4350",
"4351",
"4352",
"4353",
"4354",
"4355",
"4356",
"4357",
"4358",
"4359",
"4360",
"4361"
],
"FPGA_beamlet_output_hdr_eth_destination_mac_RW_default": [ "FPGA_beamlet_output_hdr_eth_destination_mac_RW_default": [
"01:23:45:67:89:AB", "01:23:45:67:89:AB",
"01:23:45:67:89:AB", "01:23:45:67:89:AB",
......
README.md
+ 1
− 0
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...@@ -105,3 +105,4 @@ Next change the version in the following places: ...@@ -105,3 +105,4 @@ Next change the version in the following places:
# Release Notes # Release Notes
* 0.1.2 Fix `StatisticsClient` accessing `last_invalid_packet_exception` parameter * 0.1.2 Fix `StatisticsClient` accessing `last_invalid_packet_exception` parameter
* 0.2.0 Extend `Beamlet` device with FPGA source address attributes
tangostationcontrol/VERSION
+ 1
− 1
View file @ 8ba94956
0.1.2 0.2.0
tangostationcontrol/tangostationcontrol/devices/sdp/beamlet.py
+ 28
− 1
View file @ 8ba94956
...@@ -43,6 +43,21 @@ class Beamlet(opcua_device): ...@@ -43,6 +43,21 @@ class Beamlet(opcua_device):
# Device Properties # Device Properties
# ----------------- # -----------------
FPGA_beamlet_output_hdr_eth_source_mac_RW_default = device_property(
dtype='DevVarStringArray',
mandatory=True
)
FPGA_beamlet_output_hdr_ip_source_address_RW_default = device_property(
dtype='DevVarStringArray',
mandatory=True
)
FPGA_beamlet_output_hdr_udp_source_port_RW_default = device_property(
dtype='DevVarUShortArray',
mandatory=True
)
FPGA_beamlet_output_hdr_eth_destination_mac_RW_default = device_property( FPGA_beamlet_output_hdr_eth_destination_mac_RW_default = device_property(
dtype='DevVarStringArray', dtype='DevVarStringArray',
mandatory=True mandatory=True
...@@ -83,6 +98,9 @@ class Beamlet(opcua_device): ...@@ -83,6 +98,9 @@ class Beamlet(opcua_device):
) )
FIRST_DEFAULT_SETTINGS = [ FIRST_DEFAULT_SETTINGS = [
'FPGA_beamlet_output_hdr_eth_source_mac_RW',
'FPGA_beamlet_output_hdr_ip_source_address_RW',
'FPGA_beamlet_output_hdr_udp_source_port_RW',
'FPGA_beamlet_output_hdr_eth_destination_mac_RW', 'FPGA_beamlet_output_hdr_eth_destination_mac_RW',
'FPGA_beamlet_output_hdr_ip_destination_address_RW', 'FPGA_beamlet_output_hdr_ip_destination_address_RW',
'FPGA_beamlet_output_hdr_udp_destination_port_RW', 'FPGA_beamlet_output_hdr_udp_destination_port_RW',
...@@ -96,12 +114,21 @@ class Beamlet(opcua_device): ...@@ -96,12 +114,21 @@ class Beamlet(opcua_device):
FPGA_beamlet_output_enable_R = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_enable_R"], datatype=bool, dims=(N_PN,)) FPGA_beamlet_output_enable_R = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_enable_R"], datatype=bool, dims=(N_PN,))
FPGA_beamlet_output_enable_RW = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_enable_RW"], datatype=bool, dims=(N_PN,), access=AttrWriteType.READ_WRITE) FPGA_beamlet_output_enable_RW = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_enable_RW"], datatype=bool, dims=(N_PN,), access=AttrWriteType.READ_WRITE)
FPGA_beamlet_output_hdr_eth_source_mac_R = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_hdr_eth_source_mac_R"], datatype=str, dims=(N_PN,))
FPGA_beamlet_output_hdr_eth_source_mac_RW = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_hdr_eth_source_mac_RW"], datatype=str, dims=(N_PN,), access=AttrWriteType.READ_WRITE)
FPGA_beamlet_output_hdr_ip_source_address_R = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_hdr_ip_source_address_R"], datatype=str, dims=(N_PN,))
FPGA_beamlet_output_hdr_ip_source_address_RW = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_hdr_ip_source_address_RW"], datatype=str, dims=(N_PN,), access=AttrWriteType.READ_WRITE)
FPGA_beamlet_output_hdr_udp_source_port_R = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_hdr_udp_source_port_R"], datatype=numpy.uint16, dims=(N_PN,))
FPGA_beamlet_output_hdr_udp_source_port_RW = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_hdr_udp_source_port_RW"], datatype=numpy.uint16, dims=(N_PN,), access=AttrWriteType.READ_WRITE)
FPGA_beamlet_output_hdr_eth_destination_mac_R = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_hdr_eth_destination_mac_R"], datatype=str, dims=(N_PN,)) FPGA_beamlet_output_hdr_eth_destination_mac_R = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_hdr_eth_destination_mac_R"], datatype=str, dims=(N_PN,))
FPGA_beamlet_output_hdr_eth_destination_mac_RW = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_hdr_eth_destination_mac_RW"], datatype=str, dims=(N_PN,), access=AttrWriteType.READ_WRITE) FPGA_beamlet_output_hdr_eth_destination_mac_RW = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_hdr_eth_destination_mac_RW"], datatype=str, dims=(N_PN,), access=AttrWriteType.READ_WRITE)
FPGA_beamlet_output_hdr_ip_destination_address_R = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_hdr_ip_destination_address_R"], datatype=str, dims=(N_PN,)) FPGA_beamlet_output_hdr_ip_destination_address_R = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_hdr_ip_destination_address_R"], datatype=str, dims=(N_PN,))
FPGA_beamlet_output_hdr_ip_destination_address_RW = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_hdr_ip_destination_address_RW"], datatype=str, dims=(N_PN,), access=AttrWriteType.READ_WRITE) FPGA_beamlet_output_hdr_ip_destination_address_RW = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_hdr_ip_destination_address_RW"], datatype=str, dims=(N_PN,), access=AttrWriteType.READ_WRITE)
FPGA_beamlet_output_hdr_udp_destination_port_R = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_hdr_udp_destination_port_R"], datatype=numpy.uint16, dims=(N_PN,)) FPGA_beamlet_output_hdr_udp_destination_port_R = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_hdr_udp_destination_port_R"], datatype=numpy.uint16, dims=(N_PN,))
FPGA_beamlet_output_hdr_udp_destination_port_RW = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_hdr_udp_destination_port_RW"], datatype=numpy.uint16, dims=(N_PN,), access=AttrWriteType.READ_WRITE) FPGA_beamlet_output_hdr_udp_destination_port_RW = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_hdr_udp_destination_port_RW"], datatype=numpy.uint16, dims=(N_PN,), access=AttrWriteType.READ_WRITE)
FPGA_beamlet_output_scale_R = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_scale_R"], datatype=numpy.double, dims=(N_PN,)) FPGA_beamlet_output_scale_R = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_scale_R"], datatype=numpy.double, dims=(N_PN,))
FPGA_beamlet_output_scale_RW = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_scale_RW"], datatype=numpy.double, dims=(N_PN,), access=AttrWriteType.READ_WRITE) FPGA_beamlet_output_scale_RW = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_scale_RW"], datatype=numpy.double, dims=(N_PN,), access=AttrWriteType.READ_WRITE)
FPGA_beamlet_output_bsn_R = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_bsn_R"], datatype=numpy.int64, dims=(N_PN, N_BEAMSETS_CTRL)) FPGA_beamlet_output_bsn_R = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_bsn_R"], datatype=numpy.int64, dims=(N_PN, N_BEAMSETS_CTRL))
......
tangostationcontrol/tangostationcontrol/integration_test/default/statistics/test_writer_sst.py
+ 1
− 1
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...@@ -82,7 +82,7 @@ class TestStatisticsWriterSST(BaseIntegrationTestCase): ...@@ -82,7 +82,7 @@ class TestStatisticsWriterSST(BaseIntegrationTestCase):
'2021-09-20T12:17:40.000+00:00' '2021-09-20T12:17:40.000+00:00'
) )
self.assertIsNotNone(stat) self.assertIsNotNone(stat)
self.assertEqual("0.1.2", stat.station_version_id) self.assertEqual("0.2.0", stat.station_version_id)
self.assertEqual("0.1", stat.writer_version_id) self.assertEqual("0.1", stat.writer_version_id)
def test_insert_tango_SST_statistics(self): def test_insert_tango_SST_statistics(self):
......
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