diff --git a/CDB/stations/CS001_ConfigDb.json b/CDB/stations/CS001_ConfigDb.json
index 56e6bb1867295475902005664deecfe1d23ad2e3..e078b8c7a9daf205a064a665a934bfb15671225b 100644
--- a/CDB/stations/CS001_ConfigDb.json
+++ b/CDB/stations/CS001_ConfigDb.json
@@ -126,6 +126,60 @@
"OPC_Time_Out": [
"5.0"
],
+ "FPGA_beamlet_output_hdr_eth_source_mac_RW_default": [
+ "00:22:86:00:01:00",
+ "00:22:86:00:01:01",
+ "00:22:86:00:01:02",
+ "00:22:86:00:01:03",
+ "00:22:86:00:01:04",
+ "00:22:86:00:01:05",
+ "00:22:86:00:01:06",
+ "00:22:86:00:01:07",
+ "00:22:86:00:01:08",
+ "00:22:86:00:01:09",
+ "00:22:86:00:01:10",
+ "00:22:86:00:01:11",
+ "00:22:86:00:01:12",
+ "00:22:86:00:01:13",
+ "00:22:86:00:01:14",
+ "00:22:86:00:01:15"
+ ],
+ "FPGA_beamlet_output_hdr_ip_source_address_RW_default": [
+ "10.175.1.0",
+ "10.175.1.1",
+ "10.175.1.2",
+ "10.175.1.3",
+ "10.175.1.4",
+ "10.175.1.5",
+ "10.175.1.6",
+ "10.175.1.7",
+ "10.175.1.8",
+ "10.175.1.9",
+ "10.175.1.10",
+ "10.175.1.11",
+ "10.175.1.12",
+ "10.175.1.13",
+ "10.175.1.14",
+ "10.175.1.15"
+ ],
+ "FPGA_beamlet_output_hdr_udp_source_port_RW_default": [
+ "4346",
+ "4347",
+ "4348",
+ "4349",
+ "4350",
+ "4351",
+ "4352",
+ "4353",
+ "4354",
+ "4355",
+ "4356",
+ "4357",
+ "4358",
+ "4359",
+ "4360",
+ "4361"
+ ],
"FPGA_beamlet_output_hdr_eth_destination_mac_RW_default": [
"3c:ec:ef:86:2f:b7",
"3c:ec:ef:86:2f:b7",
diff --git a/CDB/stations/simulators_ConfigDb.json b/CDB/stations/simulators_ConfigDb.json
index 51ea376830d859c5d8aab806841e2826e73a669e..f67bac70383d93f8fcb3b5c14b48727ea1368de3 100644
--- a/CDB/stations/simulators_ConfigDb.json
+++ b/CDB/stations/simulators_ConfigDb.json
@@ -84,6 +84,60 @@
"OPC_Time_Out": [
"5.0"
],
+ "FPGA_beamlet_output_hdr_eth_source_mac_RW_default": [
+ "00:11:22:33:44:00",
+ "00:11:22:33:44:01",
+ "00:11:22:33:44:02",
+ "00:11:22:33:44:03",
+ "00:11:22:33:44:04",
+ "00:11:22:33:44:05",
+ "00:11:22:33:44:06",
+ "00:11:22:33:44:07",
+ "00:11:22:33:44:08",
+ "00:11:22:33:44:09",
+ "00:11:22:33:44:10",
+ "00:11:22:33:44:11",
+ "00:11:22:33:44:12",
+ "00:11:22:33:44:13",
+ "00:11:22:33:44:14",
+ "00:11:22:33:44:15"
+ ],
+ "FPGA_beamlet_output_hdr_ip_source_address_RW_default": [
+ "10.0.0.0",
+ "10.0.0.1",
+ "10.0.0.2",
+ "10.0.0.3",
+ "10.0.0.4",
+ "10.0.0.5",
+ "10.0.0.6",
+ "10.0.0.7",
+ "10.0.0.8",
+ "10.0.0.9",
+ "10.0.0.10",
+ "10.0.0.11",
+ "10.0.0.12",
+ "10.0.0.13",
+ "10.0.0.14",
+ "10.0.0.15"
+ ],
+ "FPGA_beamlet_output_hdr_udp_source_port_RW_default": [
+ "4346",
+ "4347",
+ "4348",
+ "4349",
+ "4350",
+ "4351",
+ "4352",
+ "4353",
+ "4354",
+ "4355",
+ "4356",
+ "4357",
+ "4358",
+ "4359",
+ "4360",
+ "4361"
+ ],
"FPGA_beamlet_output_hdr_eth_destination_mac_RW_default": [
"01:23:45:67:89:AB",
"01:23:45:67:89:AB",
diff --git a/README.md b/README.md
index cb44d8f3aebe5a1c2a47239eda784959da4ca0c7..57ed52816e57541249ed224d5a5d2260c469c2e4 100644
--- a/README.md
+++ b/README.md
@@ -105,3 +105,4 @@ Next change the version in the following places:
# Release Notes
* 0.1.2 Fix `StatisticsClient` accessing `last_invalid_packet_exception` parameter
+* 0.2.0 Extend `Beamlet` device with FPGA source address attributes
diff --git a/tangostationcontrol/VERSION b/tangostationcontrol/VERSION
index d917d3e26adc9854b4569871e20111c38de2606f..0ea3a944b399d25f7e1b8fe684d754eb8da9fe7f 100644
--- a/tangostationcontrol/VERSION
+++ b/tangostationcontrol/VERSION
@@ -1 +1 @@
-0.1.2
+0.2.0
diff --git a/tangostationcontrol/tangostationcontrol/devices/sdp/beamlet.py b/tangostationcontrol/tangostationcontrol/devices/sdp/beamlet.py
index 24dda0332e8711ffd5b67226f4a7d4b1bdc1e2d3..e09ca096895cadbe9efc0e869f2c1322bc855a74 100644
--- a/tangostationcontrol/tangostationcontrol/devices/sdp/beamlet.py
+++ b/tangostationcontrol/tangostationcontrol/devices/sdp/beamlet.py
@@ -43,6 +43,21 @@ class Beamlet(opcua_device):
# Device Properties
# -----------------
+ FPGA_beamlet_output_hdr_eth_source_mac_RW_default = device_property(
+ dtype='DevVarStringArray',
+ mandatory=True
+ )
+
+ FPGA_beamlet_output_hdr_ip_source_address_RW_default = device_property(
+ dtype='DevVarStringArray',
+ mandatory=True
+ )
+
+ FPGA_beamlet_output_hdr_udp_source_port_RW_default = device_property(
+ dtype='DevVarUShortArray',
+ mandatory=True
+ )
+
FPGA_beamlet_output_hdr_eth_destination_mac_RW_default = device_property(
dtype='DevVarStringArray',
mandatory=True
@@ -83,6 +98,9 @@ class Beamlet(opcua_device):
)
FIRST_DEFAULT_SETTINGS = [
+ 'FPGA_beamlet_output_hdr_eth_source_mac_RW',
+ 'FPGA_beamlet_output_hdr_ip_source_address_RW',
+ 'FPGA_beamlet_output_hdr_udp_source_port_RW',
'FPGA_beamlet_output_hdr_eth_destination_mac_RW',
'FPGA_beamlet_output_hdr_ip_destination_address_RW',
'FPGA_beamlet_output_hdr_udp_destination_port_RW',
@@ -95,13 +113,22 @@ class Beamlet(opcua_device):
# ----------
FPGA_beamlet_output_enable_R = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_enable_R"], datatype=bool, dims=(N_PN,))
- FPGA_beamlet_output_enable_RW = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_enable_RW"], datatype=bool, dims=(N_PN,), access=AttrWriteType.READ_WRITE)
+ FPGA_beamlet_output_enable_RW = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_enable_RW"], datatype=bool, dims=(N_PN,), access=AttrWriteType.READ_WRITE)
+
+ FPGA_beamlet_output_hdr_eth_source_mac_R = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_hdr_eth_source_mac_R"], datatype=str, dims=(N_PN,))
+ FPGA_beamlet_output_hdr_eth_source_mac_RW = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_hdr_eth_source_mac_RW"], datatype=str, dims=(N_PN,), access=AttrWriteType.READ_WRITE)
+ FPGA_beamlet_output_hdr_ip_source_address_R = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_hdr_ip_source_address_R"], datatype=str, dims=(N_PN,))
+ FPGA_beamlet_output_hdr_ip_source_address_RW = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_hdr_ip_source_address_RW"], datatype=str, dims=(N_PN,), access=AttrWriteType.READ_WRITE)
+ FPGA_beamlet_output_hdr_udp_source_port_R = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_hdr_udp_source_port_R"], datatype=numpy.uint16, dims=(N_PN,))
+ FPGA_beamlet_output_hdr_udp_source_port_RW = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_hdr_udp_source_port_RW"], datatype=numpy.uint16, dims=(N_PN,), access=AttrWriteType.READ_WRITE)
+
FPGA_beamlet_output_hdr_eth_destination_mac_R = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_hdr_eth_destination_mac_R"], datatype=str, dims=(N_PN,))
FPGA_beamlet_output_hdr_eth_destination_mac_RW = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_hdr_eth_destination_mac_RW"], datatype=str, dims=(N_PN,), access=AttrWriteType.READ_WRITE)
FPGA_beamlet_output_hdr_ip_destination_address_R = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_hdr_ip_destination_address_R"], datatype=str, dims=(N_PN,))
FPGA_beamlet_output_hdr_ip_destination_address_RW = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_hdr_ip_destination_address_RW"], datatype=str, dims=(N_PN,), access=AttrWriteType.READ_WRITE)
FPGA_beamlet_output_hdr_udp_destination_port_R = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_hdr_udp_destination_port_R"], datatype=numpy.uint16, dims=(N_PN,))
FPGA_beamlet_output_hdr_udp_destination_port_RW = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_hdr_udp_destination_port_RW"], datatype=numpy.uint16, dims=(N_PN,), access=AttrWriteType.READ_WRITE)
+
FPGA_beamlet_output_scale_R = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_scale_R"], datatype=numpy.double, dims=(N_PN,))
FPGA_beamlet_output_scale_RW = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_scale_RW"], datatype=numpy.double, dims=(N_PN,), access=AttrWriteType.READ_WRITE)
FPGA_beamlet_output_bsn_R = attribute_wrapper(comms_annotation=["FPGA_beamlet_output_bsn_R"], datatype=numpy.int64, dims=(N_PN, N_BEAMSETS_CTRL))
diff --git a/tangostationcontrol/tangostationcontrol/integration_test/default/statistics/test_writer_sst.py b/tangostationcontrol/tangostationcontrol/integration_test/default/statistics/test_writer_sst.py
index 4a1114d44947591ddb1a765662db5590c4ca16d9..89eb31d8ef6db7f74345aab8b0ba7bf35de741e1 100644
--- a/tangostationcontrol/tangostationcontrol/integration_test/default/statistics/test_writer_sst.py
+++ b/tangostationcontrol/tangostationcontrol/integration_test/default/statistics/test_writer_sst.py
@@ -82,7 +82,7 @@ class TestStatisticsWriterSST(BaseIntegrationTestCase):
'2021-09-20T12:17:40.000+00:00'
)
self.assertIsNotNone(stat)
- self.assertEqual("0.1.2", stat.station_version_id)
+ self.assertEqual("0.2.0", stat.station_version_id)
self.assertEqual("0.1", stat.writer_version_id)
def test_insert_tango_SST_statistics(self):