Provide a default of 0 for the signal input samples delay, as part of...

Provide a default of 0 for the signal input samples delay, as part of initialising to a well-defined state.

tangostationcontrol/tangostationcontrol/devices/sdp/sdp.py

@@ -78,6 +78,12 @@ class SDP(opcua_device):
         default_value=[0] * 16
     )
 
+    FPGA_signal_input_samples_delay_RW_default = device_property(
+        dtype='DevVarULongArray',
+        mandatory=False,
+        default_value=[[0] * 12] * 16
+    )
+
     FPGA_subband_weights_RW_default = device_property(
         dtype='DevVarULongArray',
         mandatory=False,