From 45f70341a1587c09557c22f35b5b86baee6a75b1 Mon Sep 17 00:00:00 2001
From: Jan David Mol <mol@astron.nl>
Date: Tue, 30 Nov 2021 17:06:04 +0100
Subject: [PATCH] Provide a default of 0 for the signal input samples delay, as
part of initialising to a well-defined state.
---
tangostationcontrol/tangostationcontrol/devices/sdp/sdp.py | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/tangostationcontrol/tangostationcontrol/devices/sdp/sdp.py b/tangostationcontrol/tangostationcontrol/devices/sdp/sdp.py
index ed970bc56..b613a3af4 100644
--- a/tangostationcontrol/tangostationcontrol/devices/sdp/sdp.py
+++ b/tangostationcontrol/tangostationcontrol/devices/sdp/sdp.py
@@ -78,6 +78,12 @@ class SDP(opcua_device):
default_value=[0] * 16
)
+ FPGA_signal_input_samples_delay_RW_default = device_property(
+ dtype='DevVarULongArray',
+ mandatory=False,
+ default_value=[[0] * 12] * 16
+ )
+
FPGA_subband_weights_RW_default = device_property(
dtype='DevVarULongArray',
mandatory=False,
--
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