Skip to content
Snippets Groups Projects
Commit 17b3304a authored by Jan David Mol's avatar Jan David Mol
Browse files

L2SS-358: Make station ID optional, give simulators some XST/SST destination... 

L2SS-358: Make station ID optional, give simulators some XST/SST destination as they're mandatory, even though the simulators will never use their value. Remove superfluous port override in LTS config
parent ebbb04da
No related branches found
No related tags found
1 merge request!157L2SS-358: Get ready for Darkrai
Hide whitespace changes
Inline Side-by-side
CDB/stations/LTS_ConfigDb.json
+ 0
− 36
View file @ 17b3304a
...@@ -158,24 +158,6 @@ ...@@ -158,24 +158,6 @@
"10.99.250.250", "10.99.250.250",
"10.99.250.250", "10.99.250.250",
"10.99.250.250" "10.99.250.250"
],
"FPGA_sst_offload_hdr_udp_destination_port_RW_default": [
"5001",
"5001",
"5001",
"5001",
"5001",
"5001",
"5001",
"5001",
"5001",
"5001",
"5001",
"5001",
"5001",
"5001",
"5001",
"5001"
] ]
} }
} }
...@@ -237,24 +219,6 @@ ...@@ -237,24 +219,6 @@
"10.99.250.250", "10.99.250.250",
"10.99.250.250", "10.99.250.250",
"10.99.250.250" "10.99.250.250"
],
"FPGA_xst_offload_hdr_udp_destination_port_RW_default": [
"5002",
"5002",
"5002",
"5002",
"5002",
"5002",
"5002",
"5002",
"5002",
"5002",
"5002",
"5002",
"5002",
"5002",
"5002",
"5002"
] ]
} }
} }
......
CDB/stations/simulators_configDb.json
+ 72
− 0
View file @ 17b3304a
...@@ -89,6 +89,42 @@ ...@@ -89,6 +89,42 @@
], ],
"OPC_Time_Out": [ "OPC_Time_Out": [
"5.0" "5.0"
],
"FPGA_sst_offload_hdr_eth_destination_mac_RW_default": [
"01:23:45:67:89:AB",
"01:23:45:67:89:AB",
"01:23:45:67:89:AB",
"01:23:45:67:89:AB",
"01:23:45:67:89:AB",
"01:23:45:67:89:AB",
"01:23:45:67:89:AB",
"01:23:45:67:89:AB",
"01:23:45:67:89:AB",
"01:23:45:67:89:AB",
"01:23:45:67:89:AB",
"01:23:45:67:89:AB",
"01:23:45:67:89:AB",
"01:23:45:67:89:AB",
"01:23:45:67:89:AB",
"01:23:45:67:89:AB"
],
"FPGA_sst_offload_hdr_ip_destination_address_RW_default": [
"127.0.0.1",
"127.0.0.1",
"127.0.0.1",
"127.0.0.1",
"127.0.0.1",
"127.0.0.1",
"127.0.0.1",
"127.0.0.1",
"127.0.0.1",
"127.0.0.1",
"127.0.0.1",
"127.0.0.1",
"127.0.0.1",
"127.0.0.1",
"127.0.0.1",
"127.0.0.1"
] ]
} }
} }
...@@ -108,6 +144,42 @@ ...@@ -108,6 +144,42 @@
], ],
"OPC_Time_Out": [ "OPC_Time_Out": [
"5.0" "5.0"
],
"FPGA_xst_offload_hdr_eth_destination_mac_RW_default": [
"01:23:45:67:89:AB",
"01:23:45:67:89:AB",
"01:23:45:67:89:AB",
"01:23:45:67:89:AB",
"01:23:45:67:89:AB",
"01:23:45:67:89:AB",
"01:23:45:67:89:AB",
"01:23:45:67:89:AB",
"01:23:45:67:89:AB",
"01:23:45:67:89:AB",
"01:23:45:67:89:AB",
"01:23:45:67:89:AB",
"01:23:45:67:89:AB",
"01:23:45:67:89:AB",
"01:23:45:67:89:AB",
"01:23:45:67:89:AB"
],
"FPGA_xst_offload_hdr_ip_destination_address_RW_default": [
"127.0.0.1",
"127.0.0.1",
"127.0.0.1",
"127.0.0.1",
"127.0.0.1",
"127.0.0.1",
"127.0.0.1",
"127.0.0.1",
"127.0.0.1",
"127.0.0.1",
"127.0.0.1",
"127.0.0.1",
"127.0.0.1",
"127.0.0.1",
"127.0.0.1",
"127.0.0.1"
] ]
} }
} }
......
devices/devices/sdp/sdp.py
+ 2
− 1
View file @ 17b3304a
...@@ -80,7 +80,8 @@ class SDP(opcua_device): ...@@ -80,7 +80,8 @@ class SDP(opcua_device):
FPGA_sdp_info_station_id_RW_default = device_property( FPGA_sdp_info_station_id_RW_default = device_property(
dtype='DevVarULongArray', dtype='DevVarULongArray',
mandatory=True mandatory=False,
default_value=[0] * 16
) )
FPGA_subband_weights_RW_default = device_property( FPGA_subband_weights_RW_default = device_property(
......
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment