Skip to content
Snippets Groups Projects

RTSD-155: vhdl_style2_0, fixed empty line and indent

Closed RTSD-155: vhdl_style2_0, fixed empty line and indent
227+ files
+ 21772
21398
Compare changes
  • Side-by-side
  • Inline

Files

@@ -30,11 +30,11 @@
-- that occurs due to shared complex FFT and seperate in PFT_MODE_REAL2.
library IEEE, common_lib, dp_lib, pfs_lib, pft2_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
use dp_lib.dp_stream_pkg.all;
use pfs_lib.pfs_pkg.all;
use pft2_lib.pft_pkg.all;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
use dp_lib.dp_stream_pkg.all;
use pfs_lib.pfs_pkg.all;
use pft2_lib.pft_pkg.all;
entity pfb2 is
generic (
@@ -88,27 +88,27 @@ begin
gen_pfs : if g_pfs_bypass = false generate
u_pfs : entity pfs_lib.pfs
generic map (
g_nof_bands => g_nof_points,
g_nof_taps => c_nof_coeffs,
g_in_dat_w => g_pfs_in_dat_w,
g_out_dat_w => g_pfs_out_dat_w,
g_coef_dat_w => g_pfs_coef_dat_w,
g_coefs_file => g_pfs_coefs_file
)
port map (
in_dat_x => pfs_in_dat_x,
in_dat_y => pfs_in_dat_y,
in_val => pfs_in_val,
in_sync => pfs_in_sync,
out_dat_x => fil_out_dat_x,
out_dat_y => fil_out_dat_y,
out_val => fil_out_val,
out_sync => fil_out_sync,
clk => dp_clk,
rst => dp_rst,
restart => '0'
);
generic map (
g_nof_bands => g_nof_points,
g_nof_taps => c_nof_coeffs,
g_in_dat_w => g_pfs_in_dat_w,
g_out_dat_w => g_pfs_out_dat_w,
g_coef_dat_w => g_pfs_coef_dat_w,
g_coefs_file => g_pfs_coefs_file
)
port map (
in_dat_x => pfs_in_dat_x,
in_dat_y => pfs_in_dat_y,
in_val => pfs_in_val,
in_sync => pfs_in_sync,
out_dat_x => fil_out_dat_x,
out_dat_y => fil_out_dat_y,
out_val => fil_out_val,
out_sync => fil_out_sync,
clk => dp_clk,
rst => dp_rst,
restart => '0'
);
end generate;
no_pfs : if g_pfs_bypass = true generate
@@ -124,26 +124,26 @@ begin
fil_sosi.sync <= fil_out_sync;
u_pft : entity pft2_lib.pft
generic map (
g_fft_size_w => ceil_log2(g_nof_points),
g_in_dat_w => g_pfs_out_dat_w,
g_out_dat_w => g_pft_out_dat_w,
g_stage_dat_w => g_pft_stage_dat_w,
g_mode => PFT_MODE_REAL2
)
port map (
in_re => fil_out_dat_x,
in_im => fil_out_dat_y,
in_val => fil_out_val,
in_sync => fil_out_sync,
switch_en => g_pft_switch_en,
out_re => pft_out_dat_re,
out_im => pft_out_dat_im,
out_val => pft_out_val,
out_sync => pft_out_sync,
clk => dp_clk,
rst => dp_rst
);
generic map (
g_fft_size_w => ceil_log2(g_nof_points),
g_in_dat_w => g_pfs_out_dat_w,
g_out_dat_w => g_pft_out_dat_w,
g_stage_dat_w => g_pft_stage_dat_w,
g_mode => PFT_MODE_REAL2
)
port map (
in_re => fil_out_dat_x,
in_im => fil_out_dat_y,
in_val => fil_out_val,
in_sync => fil_out_sync,
switch_en => g_pft_switch_en,
out_re => pft_out_dat_re,
out_im => pft_out_dat_im,
out_val => pft_out_val,
out_sync => pft_out_sync,
clk => dp_clk,
rst => dp_rst
);
-- Delay pft sync with respect pft data to fit DP sync timing
out_sosi.re <= RESIZE_DP_DSP_DATA(pft_out_dat_re);
Loading