Pieter Donker
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir.vhd
 library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
+  use IEEE.std_logic_1164.all;
+  use IEEE.numeric_std.all;

 entity pfs_fir is
  generic (
    g_in_dat_w          : natural;
    g_out_dat_w         : natural;
    g_coef_dat_w        : natural;
--    g_nof_fir           : NATURAL;
--    g_nof_subbands      : NATURAL;
+    --    g_nof_fir           : NATURAL;
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl(rtl).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl(rtl).vhd

    if unsigned(prefilter_cnt) = (g_nof_prefilter - 1) and last_tap = '1' then
      nxt_taps_addr_base <=
-          std_logic_vector(unsigned(taps_addr_base) + 1);
+      std_logic_vector(unsigned(taps_addr_base) + 1);
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl(rtl).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl(rtl).vhd

    if unsigned(prefilter_cnt) = (g_nof_prefilter - 1) and last_tap = '1' then
      nxt_taps_addr_base <=
-          std_logic_vector(unsigned(taps_addr_base) + 1);
+      std_logic_vector(unsigned(taps_addr_base) + 1);
    end if;
  end process;

  taps_addr_offset <= std_logic_vector(unsigned(taps_addr_base)
-      + unsigned(taps_cnt));
+  + unsigned(taps_cnt));
--- a/applications/lofar1/RSP/pfs/tb/vhdl/tb_pfs.vhd
+++ b/applications/lofar1/RSP/pfs/tb/vhdl/tb_pfs.vhd
      for j in 1 to 16 loop
        for i in 1 to 1024 loop
          if j = 1 then
-            in_dat_x <= TO_UVEC(2**10, in_dat_x'length);
+            in_dat_x <= TO_UVEC(2 ** 10, in_dat_x'length);
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft(str).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft(str).vhd
-        end if;
+  determine_bin : process (clk)
+  begin
+    if rising_edge(clk) then
+      if unswitch_val = '1' then
+        bin <= std_logic_vector(unsigned(bin) + 1);
      end if;
-    end process;
+    end if;
+  end process;

-    band  <= bin(bin'high downto 1);
+  band  <= bin(bin'high downto 1);

-    power <= std_logic_vector(   signed(unswitch_re) * signed(unswitch_re)
+  power <= std_logic_vector(   signed(unswitch_re) * signed(unswitch_re)
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf(rtl).vhd
+        nxt_fifo_dat <= wr_dat & fifo_dat(fifo_dat'high downto 1);
+      end if;
+      rd_dat <= fifo_dat(0);
+    end process;
  end generate;

  fifo3_gen : if c_regbank_size = c_pipeline generate
-  fifo3_reg : process (clk, rst)
-  begin
-    if rst = '1' then
-      fifo_dat <= (others => (others => '0'));
-    elsif rising_edge(clk) then
-      fifo_dat <= nxt_fifo_dat;
-    end if;
-  end process;

--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd
+        rd_req => rd_req,
+        clk    => clk,
+        rst    => rst
+      );
  end generate fifo_gen;

  fifo2_gen : if c_regbank_size > c_pipeline and c_regbank_size <= 8 generate
-  fifo2_reg : process (clk, rst)
-  begin
-    if rst = '1' then
-      fifo_dat <= (others => (others => '0'));
-    elsif rising_edge(clk) then
-      fifo_dat <= nxt_fifo_dat;
-    end if;
-  end process;

--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_stage.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_stage.vhd
+        in_sync        => bf2_sync,
+        out_re         => out_re,
+        out_im         => out_im,
+        out_val        => out_val,
+        out_sync       => out_sync,
+        clk            => clk,
+        rst            => rst
+      );
  end generate;

  gen_last: if g_index = 0 generate
    signal reg_val  : std_logic;
    signal reg_sync : std_logic;

-  begin
+    begin
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult(rtl).vhd
-
-  signal mult_out_re        : std_logic_vector(c_mult_out_w - 1 downto 0);
-  signal mult_out_im        : std_logic_vector(c_mult_out_w - 1 downto 0);
-
-  signal coeff_dat          : std_logic_vector(2 * c_coeff_w - 1 downto 0);
-  signal coeff_re           : std_logic_vector(c_coeff_w - 1 downto 0);
-  signal coeff_im           : std_logic_vector(c_coeff_w - 1 downto 0);
+  constant c_twid_rom : t_c_mem := (
+    latency  => 2,
+    adr_w    => c_adr_w,
+    dat_w    => 2 * c_coeff_w,  -- complex
+    nof_dat  => 3 * c_nof_twids / 4,  -- <= 2**g_addr_w
+    init_sl  => '0');
+
+    constant c_twid_file      : string  :=
+       "data/twiddle_" & natural'image(c_coeff_w)
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_bdo_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_bdo_pkg.vhd
  constant c_sdp_bdo_reorder_nof_blocks_max : natural := 16;
  constant c_sdp_bdo_reorder_nof_blocks_w   : natural := ceil_log2(c_sdp_bdo_reorder_nof_blocks_max + 1);
  constant c_sdp_bdo_reorder_nof_ch_max     : natural := c_sdp_bdo_reorder_nof_blocks_max *
-                                                         c_sdp_nof_beamlets_per_block *
-                                                         c_sdp_nof_words_per_beamlet;  -- = 7808
+    c_sdp_nof_beamlets_per_block *
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_bdo_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_bdo_pkg.vhd

  constant c_sdp_bdo_destinations_info_rst : t_sdp_bdo_destinations_info :=
    ( (others => (others => '0')),