Pinning check unb2c using e2sg IP and Quartus 19.4

Closes L2SDP-103

Two pinning designs unb2c_test_pinning and unb2c_test_pinning_jesd204b were synthesized and fitted in Q19.4 using the schematic-derived files TOPLEVEL_FPGA.qsf and TOPLEVEL_FPGA_JESD.qsf respectively. In order to compile the designs, placeholder hdllib.cfg and compile_ip.tcl files were created for the e2sg/altera_libraries/* IPs

Further work will be needed to: Check use of signal S10_ETH_CLK Check final placement of JESD inputs within the BCK_RX transceiver array Re-check any signal swaps during layout Re-try dual eth1g ports if needed

applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd

@@ -263,7 +263,9 @@ BEGIN
 
       rom_system_info_reset_export              => OPEN,
       rom_system_info_clk_export                => OPEN,
-      rom_system_info_address_export            => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0), 
+--    ToDo: This has changed in the peripherals package
+      rom_system_info_address_export            => rom_unb_system_info_mosi.address(9 DOWNTO 0), 
+--      rom_system_info_address_export            => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0), 
       rom_system_info_write_export              => rom_unb_system_info_mosi.wr,
       rom_system_info_writedata_export          => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
       rom_system_info_read_export               => rom_unb_system_info_mosi.rd,
@@ -279,7 +281,9 @@ BEGIN
 
       pio_pps_reset_export                      => OPEN,
       pio_pps_clk_export                        => OPEN,
-      pio_pps_address_export                    => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
+--    ToDo: This has changed in the peripherals package
+      pio_pps_address_export                    => reg_ppsh_mosi.address(0 DOWNTO 0),
+--      pio_pps_address_export                    => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
       pio_pps_write_export                      => reg_ppsh_mosi.wr,
       pio_pps_writedata_export                  => reg_ppsh_mosi.wrdata(c_word_w-1 DOWNTO 0),
       pio_pps_read_export                       => reg_ppsh_mosi.rd,