Pinning check unb2c using e2sg IP and Quartus 19.4

Closes L2SDP-103

Two pinning designs unb2c_test_pinning and unb2c_test_pinning_jesd204b were synthesized and fitted in Q19.4 using the schematic-derived files TOPLEVEL_FPGA.qsf and TOPLEVEL_FPGA_JESD.qsf respectively. In order to compile the designs, placeholder hdllib.cfg and compile_ip.tcl files were created for the e2sg/altera_libraries/* IPs

Further work will be needed to: Check use of signal S10_ETH_CLK Check final placement of JESD inputs within the BCK_RX transceiver array Re-check any signal swaps during layout Re-try dual eth1g ports if needed