Commits · a0e87e618106d762d06ebc53ca352e3dbd892439 · RTSD / HDL · GitLab

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May 22, 2015
- Added global clock buffer IP · a0e87e61
  Eric Kooistra authored 10 years ago
  
  a0e87e61
- Added fractional PLL IP with similar c0, c1 and c2 as the pll_clk200 IO PLL. · 720496f7
  Eric Kooistra authored 10 years ago
  
  720496f7
May 21, 2015
- CHanged default to stratixiv · e2f84ac7
  Pepping authored 10 years ago
  
  e2f84ac7
May 20, 2015
- Updated all IP related files to match Quartus 15.0 which uses libraries with... · 6237fca5
  Eric Kooistra authored 10 years ago
  6237fca5
Feb 03, 2015
- Back to default have c_tech_select_default = c_tech_stratixiv for UniBoard1 in SVN. · 8264be27
  Eric Kooistra authored 10 years ago
  
  8264be27
Jan 09, 2015
- fix library quartus setting 140 -> 141 · a947d6dd
  Kenneth Hiemstra authored 10 years ago
  
  a947d6dd
Dec 11, 2014
- accidently changed to arria10. now default back to stratix · 13874ad7
  Kenneth Hiemstra authored 10 years ago
  
  13874ad7
Dec 05, 2014
- added the "pll_clk200" ip block · 277fc9df
  Kenneth Hiemstra authored 10 years ago
  
  277fc9df
Oct 31, 2014
- Added commented c_tech_arria10. · 4de55ce8
  Eric Kooistra authored 10 years ago
  
  4de55ce8
Jun 05, 2014
- Moved technology_pkg.vhd and technology_select_pkg.vhd from base/ to . and remove base/. · 9c655ef0
  Eric Kooistra authored 11 years ago
  9c655ef0
May 27, 2014
- Ported common RAM, ROM components from... · 901887ef
  Eric Kooistra authored 11 years ago
  901887ef