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RTSD
HDL
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Commits · a0a9e860ebcaab67c3493f5c060499967309e4d9
a0a9e860ebcaab67c3493f5c060499967309e4d9
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a0a9e860ebcaab67c3493f5c060499967309e4d9
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L2SDP-LIFT
L2SDP-1137
L2SDP-1113
HPR-158
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hdl
libraries
technology
ddr
tech_ddr_mem_model_component_pkg.vhd
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authors
Daniel van der Schuur
schuur
Eric Kooistra
kooistra
Gijs Schoonderbeek
schoonderbeek
Pieter Donker
donker
Steven van der Vlugt
vlugt
5 authors
Browse files
Jan 20, 2015
Added 4GByte DDR4 memory model for 1600 Mtransfers/s.
· 30bdacdd
Eric Kooistra
authored
Jan 20, 2015
30bdacdd
Dec 19, 2014
Added ddr3 memory model for simulation. The model comes from an example design in ip_stratixiv
· bc5e1243
Eric Kooistra
authored
Dec 19, 2014
bc5e1243
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Eric Kooistra authored
Eric Kooistra authored