Commits · 7d055f4be3374061583d5f856f758f356eda522c · RTSD / HDL · GitLab

Snippets Groups Projects

Mar 19, 2024
- added qsfp_leds_v2 and connected the DDR cal OK signal. · 7d055f4b
  Reinier van der Walle authored Mar 19, 2024
  7d055f4b
Aug 21, 2023
- RTSD-154 : fix with vhdl_style_fix empty lines · f362cb95
  Pieter Donker authored Aug 21, 2023
  
  f362cb95
Aug 16, 2023
- Revert "Merge branch 'RTSD-82 ' into 'master'" · 1dc76b73
  Pieter Donker authored Aug 16, 2023
  1dc76b73
- RTSD-82 : add indent fix from vsg · 848a1d38
  Pieter Donker authored Aug 16, 2023
  
  848a1d38
Jun 14, 2023
- RTSD-93 , master with all style fixes · de83af40
  Pieter Donker authored Jun 14, 2023
  
  de83af40
Oct 18, 2015
- Added and pass on g_technology. · 9c281f47
  Eric Kooistra authored Oct 18, 2015
  
  9c281f47
Jun 26, 2015
- Use separate g_dp_wr_fifo_depth and g_dp_rd_fifo_depth. · fbadd894
  Eric Kooistra authored Jun 26, 2015
  
  fbadd894
- Derive g_rd_fifo_af_margin internally in io_ddr.vhd based on g_tech_ddr.name=DDR3 or DDR4. · 12fd53ea
  Eric Kooistra authored Jun 26, 2015
  
  12fd53ea
Jun 25, 2015
- Removed dvr_clk, because it is the mm_clk. Fixed use g_cross_domain_dvr_ctlr =... · 755f1acb
  Eric Kooistra authored Jun 25, 2015
  755f1acb
Jun 12, 2015
- Added g_sim_model. · 33e83b5a
  Eric Kooistra authored Jun 12, 2015
  
  33e83b5a
- Provide streaming access to IO_DDR using a Tx seq and a Rx seq with optional DB RAM. · 61f16974
  Eric Kooistra authored Jun 12, 2015
  
  61f16974
Jun 11, 2015
- Added draft src/vhdl/mms_io_ddr_diag.vhd, it intstantiates the BG, DB and... · 4e1d928d
  Eric Kooistra authored Jun 11, 2015
  4e1d928d