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Commit fef816dd authored by Eric Kooistra's avatar Eric Kooistra
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Use c_mon_sync_latency to account for sync_reg2 pipeline in dp_bsn_monitor_v2.

parent 45bffe52
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1 merge request!288Resolve L2SDP-836
...@@ -80,6 +80,7 @@ ARCHITECTURE tb OF tb_mmp_dp_bsn_align_v2 IS ...@@ -80,6 +80,7 @@ ARCHITECTURE tb OF tb_mmp_dp_bsn_align_v2 IS
CONSTANT c_nof_clk_per_sync : NATURAL := c_block_per_sync * c_block_period; CONSTANT c_nof_clk_per_sync : NATURAL := c_block_per_sync * c_block_period;
CONSTANT c_nof_input_bsn_monitors : NATURAL := c_nof_streams; CONSTANT c_nof_input_bsn_monitors : NATURAL := c_nof_streams;
CONSTANT c_use_bsn_output_monitor : BOOLEAN := TRUE; CONSTANT c_use_bsn_output_monitor : BOOLEAN := TRUE;
CONSTANT c_mon_sync_latency : NATURAL := 1; -- due to sync_reg2 in dp_bsn_monitor_v2
CONSTANT c_reg_bsn_monitor_adr_w : NATURAL := ceil_log2(7); CONSTANT c_reg_bsn_monitor_adr_w : NATURAL := ceil_log2(7);
CONSTANT c_reg_bsn_monitor_span : NATURAL := 2**c_reg_bsn_monitor_adr_w; CONSTANT c_reg_bsn_monitor_span : NATURAL := 2**c_reg_bsn_monitor_adr_w;
...@@ -216,7 +217,8 @@ BEGIN ...@@ -216,7 +217,8 @@ BEGIN
FOR I IN 0 TO c_nof_streams-1 LOOP FOR I IN 0 TO c_nof_streams-1 LOOP
proc_mem_mm_bus_rd(2*I, mm_clk, reg_bsn_align_cipo, reg_bsn_align_copi); proc_mem_mm_bus_rd(2*I, mm_clk, reg_bsn_align_cipo, reg_bsn_align_copi);
proc_mem_mm_bus_rd_latency(1, mm_clk); proc_mem_mm_bus_rd_latency(1, mm_clk);
ASSERT reg_bsn_align_cipo.rddata(0) = '1' REPORT "Wrong stream disable for output " & int_to_str(I) SEVERITY ERROR; ASSERT reg_bsn_align_cipo.rddata(0) = '1' REPORT
"Wrong stream disable for output " & int_to_str(I) SEVERITY ERROR;
END LOOP; END LOOP;
-- Write stream enable bits for stream_en_arr -- Write stream enable bits for stream_en_arr
...@@ -230,7 +232,8 @@ BEGIN ...@@ -230,7 +232,8 @@ BEGIN
FOR I IN 0 TO c_nof_streams-1 LOOP FOR I IN 0 TO c_nof_streams-1 LOOP
proc_mem_mm_bus_rd(2*I, mm_clk, reg_bsn_align_cipo, reg_bsn_align_copi); proc_mem_mm_bus_rd(2*I, mm_clk, reg_bsn_align_cipo, reg_bsn_align_copi);
proc_mem_mm_bus_rd_latency(1, mm_clk); proc_mem_mm_bus_rd_latency(1, mm_clk);
ASSERT reg_bsn_align_cipo.rddata(0) = '0' REPORT "Wrong BSN align stream enable for output " & int_to_str(I) SEVERITY ERROR; ASSERT reg_bsn_align_cipo.rddata(0) = '0' REPORT
"Wrong BSN align stream enable for output " & int_to_str(I) SEVERITY ERROR;
END LOOP; END LOOP;
-- Write stream enable bits for stream_en_arr -- Write stream enable bits for stream_en_arr
...@@ -244,7 +247,8 @@ BEGIN ...@@ -244,7 +247,8 @@ BEGIN
FOR I IN 0 TO c_nof_streams-1 LOOP FOR I IN 0 TO c_nof_streams-1 LOOP
proc_mem_mm_bus_rd(2*I, mm_clk, reg_bsn_align_cipo, reg_bsn_align_copi); proc_mem_mm_bus_rd(2*I, mm_clk, reg_bsn_align_cipo, reg_bsn_align_copi);
proc_mem_mm_bus_rd_latency(1, mm_clk); proc_mem_mm_bus_rd_latency(1, mm_clk);
ASSERT reg_bsn_align_cipo.rddata(0) = '1' REPORT "Wrong BSN align stream enable for output " & int_to_str(I) SEVERITY ERROR; ASSERT reg_bsn_align_cipo.rddata(0) = '1' REPORT
"Wrong BSN align stream enable for output " & int_to_str(I) SEVERITY ERROR;
END LOOP; END LOOP;
-- End of MM test -- End of MM test
...@@ -253,6 +257,7 @@ BEGIN ...@@ -253,6 +257,7 @@ BEGIN
END PROCESS; END PROCESS;
p_mm_verify_bsn_monitors : PROCESS p_mm_verify_bsn_monitors : PROCESS
VARIABLE v_exp_latency : INTEGER;
BEGIN BEGIN
proc_common_wait_until_high(mm_clk, verify_done); proc_common_wait_until_high(mm_clk, verify_done);
...@@ -263,11 +268,19 @@ BEGIN ...@@ -263,11 +268,19 @@ BEGIN
mon_latency_input_arr(I) <= TO_SINT(reg_input_monitor_cipo.rddata(31 DOWNTO 0)); mon_latency_input_arr(I) <= TO_SINT(reg_input_monitor_cipo.rddata(31 DOWNTO 0));
proc_common_wait_some_cycles(mm_clk, 1); proc_common_wait_some_cycles(mm_clk, 1);
IF g_lost_input = TRUE AND I = c_nof_streams-1 THEN IF g_lost_input = TRUE AND I = c_nof_streams-1 THEN
ASSERT mon_latency_input_arr(I) = -1 REPORT "Wrong input BSN monitor latency timeout for input " & int_to_str(I) & v_exp_latency := -1; -- -1 for BSN monitor timeout due to lost input
" (" & int_to_str(mon_latency_input_arr(I)) & " /= -1)" SEVERITY ERROR; ASSERT mon_latency_input_arr(I) = v_exp_latency REPORT
"Wrong input BSN monitor latency timeout for input " & int_to_str(I) &
" (" & int_to_str(mon_latency_input_arr(I)) &
" /= " & int_to_str(v_exp_latency) &
")" SEVERITY ERROR;
ELSE ELSE
ASSERT mon_latency_input_arr(I) = func_input_delay(I) REPORT "Wrong input BSN monitor latency for input " & int_to_str(I) & v_exp_latency := c_mon_sync_latency + func_input_delay(I);
" (" & int_to_str(mon_latency_input_arr(I)) & " /= " & int_to_str(func_input_delay(I)) & ")" SEVERITY ERROR; ASSERT mon_latency_input_arr(I) = v_exp_latency REPORT
"Wrong input BSN monitor latency for input " & int_to_str(I) &
" (" & int_to_str(mon_latency_input_arr(I)) &
" /= " & int_to_str(v_exp_latency) &
")" SEVERITY ERROR;
END IF; END IF;
END LOOP; END LOOP;
...@@ -277,7 +290,11 @@ BEGIN ...@@ -277,7 +290,11 @@ BEGIN
mon_latency_output <= TO_SINT(reg_output_monitor_cipo.rddata(31 DOWNTO 0)); mon_latency_output <= TO_SINT(reg_output_monitor_cipo.rddata(31 DOWNTO 0));
proc_common_wait_some_cycles(mm_clk, 1); proc_common_wait_some_cycles(mm_clk, 1);
ASSERT mon_latency_output = c_total_latency REPORT "Wrong output BSN monitor latency" SEVERITY ERROR; v_exp_latency := c_mon_sync_latency + c_total_latency;
ASSERT mon_latency_output = v_exp_latency REPORT
"Wrong output BSN monitor latency (" & int_to_str(mon_latency_output) &
" /= " & int_to_str(v_exp_latency) &
")" SEVERITY ERROR;
-- End of MM test -- End of MM test
mm_end <= '1'; mm_end <= '1';
......
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