diff --git a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd
index c66a1b87fd2f9a1803d06e30dacd2c89a8f2f11a..fc46753c9debdd6578358bdf47a2b7b7f5c20b18 100644
--- a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd
@@ -80,6 +80,7 @@ ARCHITECTURE tb OF tb_mmp_dp_bsn_align_v2 IS
   CONSTANT c_nof_clk_per_sync           : NATURAL := c_block_per_sync * c_block_period;
   CONSTANT c_nof_input_bsn_monitors     : NATURAL := c_nof_streams;
   CONSTANT c_use_bsn_output_monitor     : BOOLEAN := TRUE;
+  CONSTANT c_mon_sync_latency           : NATURAL := 1;  -- due to sync_reg2 in dp_bsn_monitor_v2
 
   CONSTANT c_reg_bsn_monitor_adr_w      : NATURAL := ceil_log2(7);
   CONSTANT c_reg_bsn_monitor_span       : NATURAL := 2**c_reg_bsn_monitor_adr_w;
@@ -216,7 +217,8 @@ BEGIN
     FOR I IN 0 TO c_nof_streams-1 LOOP
       proc_mem_mm_bus_rd(2*I, mm_clk, reg_bsn_align_cipo, reg_bsn_align_copi);
       proc_mem_mm_bus_rd_latency(1, mm_clk);
-      ASSERT reg_bsn_align_cipo.rddata(0) = '1' REPORT "Wrong stream disable for output " & int_to_str(I) SEVERITY ERROR;
+      ASSERT reg_bsn_align_cipo.rddata(0) = '1' REPORT
+        "Wrong stream disable for output " & int_to_str(I) SEVERITY ERROR;
     END LOOP;
 
     -- Write stream enable bits for stream_en_arr
@@ -230,7 +232,8 @@ BEGIN
     FOR I IN 0 TO c_nof_streams-1 LOOP
       proc_mem_mm_bus_rd(2*I, mm_clk, reg_bsn_align_cipo, reg_bsn_align_copi);
       proc_mem_mm_bus_rd_latency(1, mm_clk);
-      ASSERT reg_bsn_align_cipo.rddata(0) = '0' REPORT "Wrong BSN align stream enable for output " & int_to_str(I) SEVERITY ERROR;
+      ASSERT reg_bsn_align_cipo.rddata(0) = '0' REPORT
+        "Wrong BSN align stream enable for output " & int_to_str(I) SEVERITY ERROR;
     END LOOP;
 
     -- Write stream enable bits for stream_en_arr
@@ -244,7 +247,8 @@ BEGIN
     FOR I IN 0 TO c_nof_streams-1 LOOP
       proc_mem_mm_bus_rd(2*I, mm_clk, reg_bsn_align_cipo, reg_bsn_align_copi);
       proc_mem_mm_bus_rd_latency(1, mm_clk);
-      ASSERT reg_bsn_align_cipo.rddata(0) = '1' REPORT "Wrong BSN align stream enable for output " & int_to_str(I) SEVERITY ERROR;
+      ASSERT reg_bsn_align_cipo.rddata(0) = '1' REPORT
+        "Wrong BSN align stream enable for output " & int_to_str(I) SEVERITY ERROR;
     END LOOP;
 
     -- End of MM test
@@ -253,6 +257,7 @@ BEGIN
   END PROCESS;
 
   p_mm_verify_bsn_monitors : PROCESS
+    VARIABLE v_exp_latency : INTEGER;
   BEGIN
     proc_common_wait_until_high(mm_clk, verify_done);
 
@@ -263,11 +268,19 @@ BEGIN
       mon_latency_input_arr(I) <= TO_SINT(reg_input_monitor_cipo.rddata(31 DOWNTO 0));
       proc_common_wait_some_cycles(mm_clk, 1);
       IF g_lost_input = TRUE AND I = c_nof_streams-1 THEN
-        ASSERT mon_latency_input_arr(I) = -1 REPORT "Wrong input BSN monitor latency timeout for input " & int_to_str(I) &
-          " (" & int_to_str(mon_latency_input_arr(I)) & " /= -1)" SEVERITY ERROR;
+        v_exp_latency := -1;  -- -1 for BSN monitor timeout due to lost input
+        ASSERT mon_latency_input_arr(I) = v_exp_latency REPORT
+          "Wrong input BSN monitor latency timeout for input " & int_to_str(I) &
+          " (" & int_to_str(mon_latency_input_arr(I)) &
+          " /= " & int_to_str(v_exp_latency) &
+          ")" SEVERITY ERROR;
       ELSE
-        ASSERT mon_latency_input_arr(I) = func_input_delay(I) REPORT "Wrong input BSN monitor latency for input " & int_to_str(I) &
-          " (" & int_to_str(mon_latency_input_arr(I)) & " /= " & int_to_str(func_input_delay(I)) & ")" SEVERITY ERROR;
+        v_exp_latency := c_mon_sync_latency + func_input_delay(I);
+        ASSERT mon_latency_input_arr(I) = v_exp_latency REPORT
+          "Wrong input BSN monitor latency for input " & int_to_str(I) &
+          " (" & int_to_str(mon_latency_input_arr(I)) &
+          " /= " & int_to_str(v_exp_latency) &
+          ")" SEVERITY ERROR;
       END IF;
     END LOOP;
 
@@ -277,7 +290,11 @@ BEGIN
     mon_latency_output <= TO_SINT(reg_output_monitor_cipo.rddata(31 DOWNTO 0));
 
     proc_common_wait_some_cycles(mm_clk, 1);
-    ASSERT mon_latency_output = c_total_latency REPORT "Wrong output BSN monitor latency" SEVERITY ERROR;
+    v_exp_latency := c_mon_sync_latency + c_total_latency;
+    ASSERT mon_latency_output = v_exp_latency REPORT
+          "Wrong output BSN monitor latency (" & int_to_str(mon_latency_output) &
+          " /= " & int_to_str(v_exp_latency) &
+          ")" SEVERITY ERROR;
 
     -- End of MM test
     mm_end <= '1';