Added register map in TB

libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd

@@ -53,6 +53,7 @@ ENTITY tb_io_ddr IS
     g_ctlr_ref_clk_period   : TIME := 5000 ps;   -- 200 MHz
     g_dvr_clk_period        : TIME := 5000 ps;   -- 50 MHz
     g_dp_clk_period         : TIME := 5000 ps;   -- 200 MHz
+    g_mm_clk_period         : TIME := 8000 ps;   -- 125 MHz
     g_dp_factor             : NATURAL := 4;      -- 1 or power of 2, c_dp_data_w = c_ctlr_data_w / g_dp_factor
     g_rd_fifo_depth         : NATURAL := 512;    -- default 256 because 32b*256 fits in 1 M9K, use larger to fit more read bursts eg. in case g_dp_factor>1
     g_block_len             : NATURAL := 2500;   -- block length for a DDR write access and read back access in number of c_ctlr_data_w words
@@ -175,10 +176,15 @@ ARCHITECTURE str of tb_io_ddr IS
   SIGNAL dvr_rst              : STD_LOGIC;
   SIGNAL dp_clk               : STD_LOGIC := '0';
   SIGNAL dp_rst               : STD_LOGIC;
+  SIGNAL mm_clk               : STD_LOGIC := '0';
+  SIGNAL mm_rst               : STD_LOGIC;
 
   SIGNAL dvr_miso             : t_mem_ctlr_miso;
   SIGNAL dvr_mosi             : t_mem_ctlr_mosi;   
   
+  SIGNAL reg_io_ddr_mosi      : t_mem_mosi := c_mem_mosi_rst;           
+  SIGNAL reg_io_ddr_miso      : t_mem_miso := c_mem_miso_rst;           
+  
   SIGNAL dvr_done             : STD_LOGIC;
   SIGNAL dvr_en               : STD_LOGIC;
   SIGNAL dvr_wr_not_rd        : STD_LOGIC;
@@ -226,6 +232,9 @@ BEGIN
   dp_clk   <= NOT dp_clk OR i_tb_end AFTER g_dp_clk_period/2; 
   dp_rst   <= '1', '0' AFTER 100 ns;
 
+  mm_clk   <= NOT mm_clk OR i_tb_end AFTER g_mm_clk_period/2; 
+  mm_rst   <= '1', '0' AFTER 100 ns;
+
   tb_end <= i_tb_end;
   
   p_stimuli : PROCESS
@@ -415,6 +424,14 @@ BEGIN
     ctlr_clk_in        => ctlr_clk,  -- connect ctlr_clk_out to ctlr_clk_in at top level to avoid potential delta-cycle differences between the same clock
     ctlr_rst_in        => ctlr_rst,
     
+    -- MM clock domain
+    mm_clk             => mm_clk,    
+    mm_rst             => mm_rst,                                          
+    
+    -- MM register map for DDR controller status info
+    reg_io_ddr_mosi    => reg_io_ddr_mosi,
+    reg_io_ddr_miso    => reg_io_ddr_miso,
+    
     -- Driver clock domain
     dvr_clk            => dvr_clk,
     dvr_rst            => dvr_rst,