Updated description of g_sim.

libraries/technology/ddr/tech_ddr_mem_model.vhd

@@ -38,7 +38,8 @@ USE work.tech_ddr_mem_model_component_pkg.ALL;
 
 ENTITY tech_ddr_memory_model IS
   GENERIC (
-    g_sim        : BOOLEAN := FALSE; --FALSE: use real memory; TRUE: use generated memory
+    g_sim        : BOOLEAN := FALSE;  -- Default FALSE: no DDR memory model instantiation, this also avoids further component evaluation by synthesis.
+                                      -- TRUE: instantiate DDR memory model for simulation;
     g_tech_ddr   : t_c_tech_ddr
   );
   PORT (