From fc4373697b2ff6710c9a54a0041ba20fd39255fd Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Wed, 25 Mar 2015 15:30:15 +0000
Subject: [PATCH] Updated description of g_sim.
---
libraries/technology/ddr/tech_ddr_mem_model.vhd | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/libraries/technology/ddr/tech_ddr_mem_model.vhd b/libraries/technology/ddr/tech_ddr_mem_model.vhd
index 99cb5b5c96..6f8f4e9a7d 100644
--- a/libraries/technology/ddr/tech_ddr_mem_model.vhd
+++ b/libraries/technology/ddr/tech_ddr_mem_model.vhd
@@ -38,7 +38,8 @@ USE work.tech_ddr_mem_model_component_pkg.ALL;
ENTITY tech_ddr_memory_model IS
GENERIC (
- g_sim : BOOLEAN := FALSE; --FALSE: use real memory; TRUE: use generated memory
+ g_sim : BOOLEAN := FALSE; -- Default FALSE: no DDR memory model instantiation, this also avoids further component evaluation by synthesis.
+ -- TRUE: instantiate DDR memory model for simulation;
g_tech_ddr : t_c_tech_ddr
);
PORT (
--
GitLab