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RTSD
HDL
Commits
fc0dabaf
Commit
fc0dabaf
authored
3 years ago
by
Eric Kooistra
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Plain Diff
Renamed c_nof_blk into c_nof_blk_min. Renamed v_extra, dbg_extra into v_accumulate, dbg_accumulate.
parent
0fac6976
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!132
Renamed proc_dp_verify_sync_v2() into overloaded proc_dp_verify_sync() and...
Changes
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libraries/base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd
+2
-2
2 additions, 2 deletions
libraries/base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd
libraries/base/dp/tb/vhdl/tb_dp_pkg.vhd
+11
-11
11 additions, 11 deletions
libraries/base/dp/tb/vhdl/tb_dp_pkg.vhd
with
13 additions
and
13 deletions
libraries/base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd
+
2
−
2
View file @
fc0dabaf
...
@@ -99,7 +99,7 @@ ARCHITECTURE tb OF tb_dp_bsn_source_v2 IS
...
@@ -99,7 +99,7 @@ ARCHITECTURE tb OF tb_dp_bsn_source_v2 IS
SIGNAL
expected_bsn
:
NATURAL
:
=
0
;
SIGNAL
expected_bsn
:
NATURAL
:
=
0
;
SIGNAL
expected_offset_bsn
:
NATURAL
:
=
0
;
SIGNAL
expected_offset_bsn
:
NATURAL
:
=
0
;
SIGNAL
dbg_nof_blk
:
NATURAL
:
=
0
;
SIGNAL
dbg_nof_blk
:
NATURAL
:
=
0
;
SIGNAL
dbg_
extra
:
NATURAL
:
=
0
;
SIGNAL
dbg_
accumulate
:
NATURAL
:
=
0
;
SIGNAL
dbg_expected_bsn
:
NATURAL
:
=
0
;
SIGNAL
dbg_expected_bsn
:
NATURAL
:
=
0
;
BEGIN
BEGIN
...
@@ -234,7 +234,7 @@ BEGIN
...
@@ -234,7 +234,7 @@ BEGIN
bs_sosi
.
sop
,
bs_sosi
.
sop
,
bs_sosi
.
bsn
,
bs_sosi
.
bsn
,
dbg_nof_blk
,
dbg_nof_blk
,
dbg_
extra
,
dbg_
accumulate
,
dbg_expected_bsn
);
dbg_expected_bsn
);
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
...
...
This diff is collapsed.
Click to expand it.
libraries/base/dp/tb/vhdl/tb_dp_pkg.vhd
+
11
−
11
View file @
fc0dabaf
...
@@ -488,7 +488,7 @@ PACKAGE tb_dp_pkg IS
...
@@ -488,7 +488,7 @@ PACKAGE tb_dp_pkg IS
SIGNAL
bsn
:
IN
STD_LOGIC_VECTOR
;
SIGNAL
bsn
:
IN
STD_LOGIC_VECTOR
;
-- for debug purposes
-- for debug purposes
SIGNAL
dbg_nof_blk
:
OUT
NATURAL
;
SIGNAL
dbg_nof_blk
:
OUT
NATURAL
;
SIGNAL
dbg_
extra
:
OUT
NATURAL
;
SIGNAL
dbg_
accumulate
:
OUT
NATURAL
;
SIGNAL
dbg_expected_bsn
:
OUT
NATURAL
);
SIGNAL
dbg_expected_bsn
:
OUT
NATURAL
);
-- Verify the DUT output sop and eop
-- Verify the DUT output sop and eop
...
@@ -2351,33 +2351,33 @@ PACKAGE BODY tb_dp_pkg IS
...
@@ -2351,33 +2351,33 @@ PACKAGE BODY tb_dp_pkg IS
SIGNAL
bsn
:
IN
STD_LOGIC_VECTOR
;
SIGNAL
bsn
:
IN
STD_LOGIC_VECTOR
;
-- for debug purposes
-- for debug purposes
SIGNAL
dbg_nof_blk
:
OUT
NATURAL
;
SIGNAL
dbg_nof_blk
:
OUT
NATURAL
;
SIGNAL
dbg_
extra
:
OUT
NATURAL
;
SIGNAL
dbg_
accumulate
:
OUT
NATURAL
;
SIGNAL
dbg_expected_bsn
:
OUT
NATURAL
)
IS
SIGNAL
dbg_expected_bsn
:
OUT
NATURAL
)
IS
CONSTANT
c_bsn_w
:
NATURAL
:
=
sel_a_b
(
bsn
'LENGTH
>
31
,
31
,
bsn
'LENGTH
);
-- use maximally c_natural_w = 31 bit of BSN slv to allow calculations with integers
CONSTANT
c_bsn_w
:
NATURAL
:
=
sel_a_b
(
bsn
'LENGTH
>
31
,
31
,
bsn
'LENGTH
);
-- use maximally c_natural_w = 31 bit of BSN slv to allow calculations with integers
CONSTANT
c_nof_blk
:
NATURAL
:
=
c_sync_period
/
c_block_size
;
-- minimum number of blocks in sync period
CONSTANT
c_nof_blk
_min
:
NATURAL
:
=
c_sync_period
/
c_block_size
;
-- minimum number of blocks in sync period
CONSTANT
c_extra
:
NATURAL
:
=
c_sync_period
MOD
c_block_size
;
-- number of extra samples in sync period
CONSTANT
c_extra
:
NATURAL
:
=
c_sync_period
MOD
c_block_size
;
-- number of extra samples in sync period
VARIABLE
v_bsn
:
NATURAL
:
=
TO_UINT
(
bsn
(
c_bsn_w
-1
DOWNTO
0
));
VARIABLE
v_bsn
:
NATURAL
:
=
TO_UINT
(
bsn
(
c_bsn_w
-1
DOWNTO
0
));
VARIABLE
v_expected_sync
:
BOOLEAN
:
=
FALSE
;
-- default FALSE, e.g. when bsn < c_start_bsn is in the past
VARIABLE
v_expected_sync
:
BOOLEAN
:
=
FALSE
;
-- default FALSE, e.g. when bsn < c_start_bsn is in the past
VARIABLE
v_expected_bsn
:
NATURAL
:
=
c_start_bsn
;
-- BSN that is expected to have a sync, intialize with start BSN
VARIABLE
v_expected_bsn
:
NATURAL
:
=
c_start_bsn
;
-- BSN that is expected to have a sync, intialize with start BSN
VARIABLE
v_nof_blk
:
NATURAL
:
=
c_nof_blk
+
1
;
-- number of blocks in period, first sync period will be 1 block longer to achieve the fraction part
VARIABLE
v_nof_blk
:
NATURAL
:
=
c_nof_blk
_min
+
1
;
-- number of blocks in period, first sync period will be 1 block longer to achieve the fraction part
VARIABLE
v_
extra
:
INTEGER
:
=
c_block_size
-
c_extra
;
-- number of extra samples in period, first sync period will have v_
extra
more
VARIABLE
v_
accumulate
:
INTEGER
:
=
c_block_size
-
c_extra
;
-- number of extra samples in period, first sync period will have v_
accumulate
more
BEGIN
BEGIN
-- Determine v_expected_sync
-- Determine v_expected_sync
IF
c_extra
=
0
THEN
IF
c_extra
=
0
THEN
-- The sync period contains an integer number of blocks (c_extra = 0)
-- The sync period contains an integer number of blocks (c_extra = 0)
-- Determine directly whether the input bsn is expected to have a sync
-- Determine directly whether the input bsn is expected to have a sync
v_expected_sync
:
=
((
v_bsn
-
c_start_bsn
)
MOD
c_nof_blk
=
0
);
v_expected_sync
:
=
((
v_bsn
-
c_start_bsn
)
MOD
c_nof_blk
_min
=
0
);
ELSE
ELSE
-- The sync period contains a fractional number of blocks
-- The sync period contains a fractional number of blocks
-- Determine next expected BSN with sync until the input bsn is reached using a loop
-- Determine next expected BSN with sync until the input bsn is reached using a loop
WHILE
v_expected_bsn
<
v_bsn
LOOP
WHILE
v_expected_bsn
<
v_bsn
LOOP
v_expected_bsn
:
=
v_expected_bsn
+
v_nof_blk
;
-- next expected BSN to have a sync
v_expected_bsn
:
=
v_expected_bsn
+
v_nof_blk
;
-- next expected BSN to have a sync
v_nof_blk
:
=
c_nof_blk
;
v_nof_blk
:
=
c_nof_blk
_min
;
v_
extra
:
=
v_extra
-
c_extra
;
v_
accumulate
:
=
v_accumulate
-
c_extra
;
IF
v_
extra
<
0
THEN
IF
v_
accumulate
<
0
THEN
v_nof_blk
:
=
v_nof_blk
+
1
;
v_nof_blk
:
=
v_nof_blk
+
1
;
v_
extra
:
=
v_extra
+
c_block_size
;
v_
accumulate
:
=
v_accumulate
+
c_block_size
;
END
IF
;
END
IF
;
END
LOOP
;
END
LOOP
;
v_expected_sync
:
=
(
v_bsn
=
v_expected_bsn
);
v_expected_sync
:
=
(
v_bsn
=
v_expected_bsn
);
...
@@ -2386,7 +2386,7 @@ PACKAGE BODY tb_dp_pkg IS
...
@@ -2386,7 +2386,7 @@ PACKAGE BODY tb_dp_pkg IS
IF
verify_en
=
'1'
THEN
IF
verify_en
=
'1'
THEN
-- Debug signals, for view in Wave window
-- Debug signals, for view in Wave window
dbg_nof_blk
<=
v_nof_blk
;
dbg_nof_blk
<=
v_nof_blk
;
dbg_
extra
<=
v_
extra
;
dbg_
accumulate
<=
v_
accumulate
;
dbg_expected_bsn
<=
v_expected_bsn
;
dbg_expected_bsn
<=
v_expected_bsn
;
END
IF
;
END
IF
;
...
...
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