Use separate g_dp_wr_fifo_depth and g_dp_rd_fifo_depth.

libraries/io/ddr/src/vhdl/mms_io_ddr_diag.vhd

@@ -32,8 +32,9 @@
 --      MM --+---------+----------+--
 --
 -- Remark:
--- . The ratio of g_dp_data_w and func_tech_ddr_ctlr_data_w(g_io_tech_ddr)must be a power of 2 due to the mixed width FIFO. By
---   using a wider g_dp_data_w the DDR data access rate can be increased to the maximum that is possible for the DDR memory.
+-- . The mixed width ratio of g_dp_data_w and ctrl_data_w=func_tech_ddr_ctlr_data_w(g_io_tech_ddr) must be a power of 2 due to the
+--   mixed width FIFO. By using a wider g_dp_data_w the DDR data access rate can be increased to the maximum that is possible for
+--   the DDR memory.
 --   - For DDR3 with ctrl_data_w = dq_w * rsl = 64 * 4 = 256 choose g_dp_data_w e.g. 16, 32, 64, 128, 256, 512.
 --   - For DDR4 with ctrl_data_w = dq_w * rsl = 72 * 8 = 576 choose g_dp_data_w e.g. 18, 36, 72, 144, 288, 576, 1152.
 -- . The DB RAM gets refilled with new read data from the DDR after the last word has been read via the MM.
@@ -56,19 +57,20 @@ USE tech_ddr_lib.tech_ddr_pkg.ALL;
 ENTITY mms_io_ddr_diag IS
   GENERIC (
     -- System
-    g_sim_model_ddr   : BOOLEAN := FALSE;
-    g_technology      : NATURAL := c_tech_select_default;
+    g_sim_model_ddr    : BOOLEAN := FALSE;
+    g_technology       : NATURAL := c_tech_select_default;
     
-    g_dp_data_w       : NATURAL := 32;  -- DP data width, func_tech_ddr_ctlr_data_w(g_io_tech_ddr)/g_dp_data_w must be a power of 2 due to the mixed width FIFO
-    g_dp_seq_dat_w    : NATURAL := 32;  -- >= 1, test sequence data width. Choose g_dp_seq_dat_w <= g_dp_data_w. The seq data gets replicated to fill g_dp_data_w.
-    g_dp_fifo_depth   : NATURAL := 2048;  -- defined at DP side of the FIFOs, write FIFO depth and read FIFO depth
+    g_dp_data_w        : NATURAL := 32;  -- DP data width, func_tech_ddr_ctlr_data_w(g_io_tech_ddr)/g_dp_data_w must be a power of 2 due to the mixed width FIFO
+    g_dp_seq_dat_w     : NATURAL := 32;  -- >= 1, test sequence data width. Choose g_dp_seq_dat_w <= g_dp_data_w. The seq data gets replicated to fill g_dp_data_w.
+    g_dp_wr_fifo_depth : NATURAL := 2048;  -- defined at DP side of the FIFO, choose 256 * (ctrl_data_w/g_dp_data_w) to make full use of M9K which have at least 256 words
+    g_dp_rd_fifo_depth : NATURAL := 2048;  -- defined at DP side of the FIFO, choose 256 * (ctrl_data_w/g_dp_data_w) or factors of 2 more to fit max number of read bursts
     
     -- IO_DDR
-    g_io_tech_ddr     : t_c_tech_ddr;
+    g_io_tech_ddr      : t_c_tech_ddr;
     
     -- DIAG data buffer
-    g_db_use_db       : BOOLEAN := FALSE;
-    g_db_buf_nof_data : NATURAL := 1024    -- nof words per data buffer
+    g_db_use_db        : BOOLEAN := FALSE;
+    g_db_buf_nof_data  : NATURAL := 1024    -- nof words per data buffer
   );
   PORT (
     ---------------------------------------------------------------------------
@@ -98,8 +100,8 @@ ENTITY mms_io_ddr_diag IS
     reg_io_ddr_miso     : OUT   t_mem_miso;
 
     -- Write / read FIFO status for monitoring purposes (in dp_clk domain)
-    wr_fifo_usedw       : OUT   STD_LOGIC_VECTOR(ceil_log2(g_dp_fifo_depth)-1 DOWNTO 0);
-    rd_fifo_usedw       : OUT   STD_LOGIC_VECTOR(ceil_log2(g_dp_fifo_depth)-1 DOWNTO 0);
+    wr_fifo_usedw       : OUT   STD_LOGIC_VECTOR(ceil_log2(g_dp_wr_fifo_depth)-1 DOWNTO 0);
+    rd_fifo_usedw       : OUT   STD_LOGIC_VECTOR(ceil_log2(g_dp_rd_fifo_depth)-1 DOWNTO 0);
 
     -- DDR3 pass on termination control from master to slave controller
     term_ctrl_out       : OUT   t_tech_ddr3_phy_terminationcontrol;
@@ -140,8 +142,8 @@ END mms_io_ddr_diag;
 
 ARCHITECTURE str OF mms_io_ddr_diag IS
 
-  CONSTANT c_io_wr_fifo_depth      : NATURAL := (g_dp_fifo_depth * g_dp_data_w) / func_tech_ddr_ctlr_data_w(g_io_tech_ddr);  -- defined at DDR side of the FIFO, >=16 and independent of wr burst size, default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
-  CONSTANT c_io_rd_fifo_depth      : NATURAL := (g_dp_fifo_depth * g_dp_data_w) / func_tech_ddr_ctlr_data_w(g_io_tech_ddr);  -- defined at DDR side of the FIFO, >=16 AND > max number of rd burst sizes (so > c_rd_fifo_af_margin), default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
+  CONSTANT c_io_wr_fifo_depth      : NATURAL := (g_dp_wr_fifo_depth * g_dp_data_w) / func_tech_ddr_ctlr_data_w(g_io_tech_ddr);  -- defined at DDR side of the FIFO, >=16 and independent of wr burst size, default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
+  CONSTANT c_io_rd_fifo_depth      : NATURAL := (g_dp_rd_fifo_depth * g_dp_data_w) / func_tech_ddr_ctlr_data_w(g_io_tech_ddr);  -- defined at DDR side of the FIFO, >=16 AND > max number of rd burst sizes (so > c_rd_fifo_af_margin), default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
     
   SIGNAL bg_siso_arr     : t_dp_siso_arr(0 DOWNTO 0) := (OTHERS=>c_dp_siso_rdy);  -- Default xon='1'
   SIGNAL bg_sosi_arr     : t_dp_sosi_arr(0 DOWNTO 0);                             -- Output SOSI that contains the waveform data