svn cp from unb_tr_10GbE. Converted to RadioHDL. Tested in frontnode.

boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg

+hdl_lib_name = unb1_tr_10GbE
+hdl_library_clause_name = unb1_tr_10GbE_lib
+hdl_lib_uses = common mm i2c unb1_board dp eth tr_xaui tr_10GbE mdio diagnostics
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+synth_files =
+    $HDL_BUILD_DIR/quartus/unb1_tr_10GbE/sopc_tr_10GbE.vhd
+    src/vhdl/node_unb1_tr_10GbE.vhd
+    src/vhdl/unb1_tr_10GbE.vhd
+    
+test_bench_files = 
+
+synth_top_level_entity =
+synth_revision = 
+
+synth_copy_files =
+    quartus/sopc_tr_10GbE.sopc .
+
+quartus_qsf_files =
+    $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+    
+quartus_tcl_files =
+    quartus/unb1_tr_10GbE_pins.tcl
+    
+quartus_vhdl_files = 
+
+quartus_qip_files =
+    $HDL_BUILD_DIR/quartus/unb1_tr_10GbE/sopc_tr_10GbE.qip
+

boards/uniboard1/designs/unb1_tr_10GbE/quartus/unb1_tr_10GbE_pins.tcl

+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_general_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_other_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
+# -- Front Interface (10GbE)
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/FRONT_NODE_tr_cntrl_pins.tcl
+
+set_location_assignment PIN_AA2 -to SA_CLK
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SA_CLK
+
+set_location_assignment PIN_M4 -to SI_FN_0_TX[0]
+set_location_assignment PIN_K4 -to SI_FN_0_TX[1]
+set_location_assignment PIN_D4 -to SI_FN_0_TX[2]
+set_location_assignment PIN_B4 -to SI_FN_0_TX[3]
+set_location_assignment PIN_N2 -to SI_FN_0_RX[0]
+set_location_assignment PIN_L2 -to SI_FN_0_RX[1]
+set_location_assignment PIN_E2 -to SI_FN_0_RX[2]
+set_location_assignment PIN_C2 -to SI_FN_0_RX[3]
+
+set_location_assignment PIN_AD4 -to SI_FN_1_TX[0]
+set_location_assignment PIN_AB4 -to SI_FN_1_TX[1]
+set_location_assignment PIN_T4 -to SI_FN_1_TX[2]
+set_location_assignment PIN_P4 -to SI_FN_1_TX[3]
+set_location_assignment PIN_AE2 -to SI_FN_1_RX[0]
+set_location_assignment PIN_AC2 -to SI_FN_1_RX[1]
+set_location_assignment PIN_U2 -to SI_FN_1_RX[2]
+set_location_assignment PIN_R2 -to SI_FN_1_RX[3]
+
+set_location_assignment PIN_AT4 -to SI_FN_2_TX[0]
+set_location_assignment PIN_AP4 -to SI_FN_2_TX[1]
+set_location_assignment PIN_AH4 -to SI_FN_2_TX[2]
+set_location_assignment PIN_AF4 -to SI_FN_2_TX[3]
+set_location_assignment PIN_AU2 -to SI_FN_2_RX[0]
+set_location_assignment PIN_AR2 -to SI_FN_2_RX[1]
+set_location_assignment PIN_AJ2 -to SI_FN_2_RX[2]
+set_location_assignment PIN_AG2 -to SI_FN_2_RX[3]
+
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_0_TX[0]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_0_TX[1]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_0_TX[2]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_0_TX[3]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_0_RX[0]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_0_RX[1]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_0_RX[2]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_0_RX[3]
+
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_1_TX[0]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_1_TX[1]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_1_TX[2]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_1_TX[3]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_1_RX[0]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_1_RX[1]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_1_RX[2]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_1_RX[3]
+
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_2_TX[0]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_2_TX[1]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_2_TX[2]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_2_TX[3]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_2_RX[0]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_2_RX[1]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_2_RX[2]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_2_RX[3]
+
+
+

boards/uniboard1/designs/unb1_tr_10GbE/src/hex/default_eth_header.hex

+:0800000000074306C7000022BF
+:0800010086080000080045001C
+:080002002322000040007F11E1
+:08000300BA530A6300010A0A66
+:080004000A0A0FA00FA0230E51
+:080005000000000000000000F3
+:080006000000000000000000F2
+:080007000000000000000000F1
+:00000001FF

boards/uniboard1/designs/unb1_tr_10GbE/src/python/gen_hex_file_dp_ram_from_mm.py

+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+from common import *
+from eth import ip_hdr_checksum
+from mem_init_file import list_to_hex
+
+# Purpose:
+# . Generate a HEX file with a default header for the RAM in tr_10GbE.vhd
+# Description:
+# . In unb_tr_10GbE, each diagnostics data block is packetized using the
+#   header in the RAM.
+# . The HEX file generated here makes up the initial RAM contents.
+# . The RAM contents can be changed during run-time using 
+#   $UPE/peripherals/pi_dp_ram_from_mm.py.
+
+###############################################################################
+# Constants
+###############################################################################
+
+FILENAME = "../hex/default_eth_header.hex"
+WORD_WIDTH = 64 # With of the 10GbE MAC's user interface
+NOF_HDR_WORDS = 8 # 512 bits = 64 bytes (c_nof_header_words in tr_10GbE.vhd)
+NOF_PAYLOAD_WORDS = 1118 # c_block_len in node_unb_tr_10GbE.vhd
+NOF_PAYLOAD_BYTES = NOF_PAYLOAD_WORDS * c_word_w / c_byte_w # 8944 bytes
+MEM_WIDTH = WORD_WIDTH
+MEM_DEPTH = NOF_HDR_WORDS
+
+# Header lengths in bytes
+ETH_HDR_LENGTH = 14
+IP_HDR_LENGTH  = 20
+UDP_HDR_LENGTH =  8
+USR_HDR_LENGTH = 22
+TOT_HDR_LENGTH = ETH_HDR_LENGTH+IP_HDR_LENGTH+UDP_HDR_LENGTH+USR_HDR_LENGTH
+
+print 'Creating Ethernet header'
+
+###############################################################################
+# Ethernet header
+###############################################################################
+eth_dst_mac = 0x00074306C700  # capture5
+eth_src_mac = 0x002286080000
+eth_type    = 0x0800
+
+eth_hdr_bytes = CommonBytes(eth_dst_mac, 6) & \
+                CommonBytes(eth_src_mac, 6) & \
+                CommonBytes(eth_type   , 2)
+
+###############################################################################
+# IP header
+###############################################################################
+ip_version         = 4 
+ip_header_length   = 5 # 5 32b words
+ip_services        = 0 
+ip_total_length    = IP_HDR_LENGTH + UDP_HDR_LENGTH + USR_HDR_LENGTH+ \
+                     NOF_PAYLOAD_BYTES
+print 'ip_total_length=',ip_total_length
+ip_total_length = 8994
+print 'ip_total_length=',ip_total_length
+
+ip_identification  = 0 
+ip_flags           = 2 
+ip_fragment_offset = 0 
+ip_time_to_live    = 127 
+ip_protocol        = 17 
+ip_header_checksum = 0 # to be calculated
+ip_src_addr        = 0x0a630001 # 10.99.0.1
+ip_dst_addr        = 0x0a0a0a0a # 10.10.10.10 # capture5
+
+ip_hdr_bits = CommonBits(ip_version         ,  4) & \
+              CommonBits(ip_header_length   ,  4) & \
+              CommonBits(ip_services        ,  8) & \
+              CommonBits(ip_total_length    , 16) & \
+              CommonBits(ip_identification  , 16) & \
+              CommonBits(ip_flags           ,  3) & \
+              CommonBits(ip_fragment_offset , 13) & \
+              CommonBits(ip_time_to_live    ,  8) & \
+              CommonBits(ip_protocol        ,  8) & \
+              CommonBits(ip_header_checksum , 16) & \
+              CommonBits(ip_src_addr        , 32) & \
+              CommonBits(ip_dst_addr        , 32)
+
+ip_hdr_bytes = CommonBytes(ip_hdr_bits.data, IP_HDR_LENGTH)
+
+# Calculate and insert the IP header checksum
+calced_checksum = ip_hdr_checksum(ip_hdr_bytes)
+print 'Inserting IP header checksum:', calced_checksum, '=', hex(calced_checksum)
+ip_hdr_bytes[9:8] = calced_checksum
+
+###############################################################################
+# UDP header
+###############################################################################
+#udp_src_port     = 0x89AB
+#udp_dst_port     = 0xCDEF
+udp_src_port     = 4000
+udp_dst_port     = 4000
+udp_total_length = USR_HDR_LENGTH + NOF_PAYLOAD_BYTES
+udp_total_length = 8974
+udp_checksum     = 0 # Zero is fine
+
+udp_hdr_bytes = CommonBytes(udp_src_port    , 2) & \
+                CommonBytes(udp_dst_port    , 2) & \
+                CommonBytes(udp_total_length, 2) & \
+                CommonBytes(udp_checksum    , 2)
+
+###############################################################################
+# USR header
+###############################################################################
+usr_hdr = 0
+usr_hdr_bytes = CommonBytes(usr_hdr, USR_HDR_LENGTH)
+
+###############################################################################
+# Total header
+###############################################################################
+tot_hdr_bytes = eth_hdr_bytes & ip_hdr_bytes & udp_hdr_bytes & usr_hdr_bytes
+
+###############################################################################
+# Convert header bytes to 64b word list
+# . The LS word of the RAM is released first. We want the MS part of the header
+#   to be released into the MAC first, so we must fill the 64b word list in 
+#   reverse.
+###############################################################################
+tot_hdr_words = CommonWords64(tot_hdr_bytes.data, NOF_HDR_WORDS)
+
+word_list = []
+for w in reversed(range(NOF_HDR_WORDS)):
+    word_list.append(tot_hdr_words[w])
+    print 'w=',w,' data=',hex(tot_hdr_words[w])
+
+###############################################################################
+# Generate the HEX file
+###############################################################################
+print 'Generating hex file:', FILENAME
+list_to_hex(word_list, FILENAME, MEM_WIDTH, MEM_DEPTH)
+print 'Done.'

boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/node_unb1_tr_10GbE.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2013
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb1_board_lib, dp_lib, tr_nonbonded_lib, tr_xaui_lib, diagnostics_lib, tr_10GbE_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE tr_xaui_lib.tr_xaui_pkg.ALL;
+
+ENTITY node_unb1_tr_10GbE IS
+  GENERIC (
+    g_sim           : BOOLEAN;
+    g_sim_level     : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model
+    g_nof_macs      : NATURAL;
+    g_use_mdio      : BOOLEAN;
+    g_mdio_epcs_dis : BOOLEAN := FALSE; -- TRUE disables EPCS on init; e.g. to target a 10GbE card in PC that does not support it
+    g_lpbk_sosi     : BOOLEAN := FALSE; --  i/o pins <-> )( <-> tr_xaui <-> )( <-> tr_10GbE <-> )( <-> user
+    g_lpbk_xgmii    : BOOLEAN := FALSE; --               ^^                 ^^                  ^^ 
+    g_lpbk_xaui     : BOOLEAN := FALSE  --    g_lpbk_xaui|      g_lpbk_xgmii|        g_lpbk_sosi|
+   );
+  PORT (
+    -- System
+    mm_rst                        : IN  STD_LOGIC;
+    mm_clk                        : IN  STD_LOGIC;
+    
+    dp_rst                        : IN  STD_LOGIC;
+    dp_clk                        : IN  STD_LOGIC;
+
+    tr_clk                        : IN  STD_LOGIC;
+    cal_rec_clk                   : IN  STD_LOGIC; 
+
+    -- MM registers
+    reg_diagnostics_mosi          : IN  t_mem_mosi;
+    reg_diagnostics_miso          : OUT t_mem_miso;
+
+    reg_hdr_insert_mosi           : IN  t_mem_mosi;
+    ram_hdr_insert_mosi           : IN  t_mem_mosi;
+
+    ram_hdr_remove_mosi           : IN  t_mem_mosi;
+    ram_hdr_remove_miso           : OUT t_mem_miso;
+
+    reg_mac_mosi                  : IN  t_mem_mosi;
+    reg_mac_miso                  : OUT t_mem_miso;
+
+    xaui_mosi                     : IN  t_mem_mosi := c_mem_mosi_rst;
+    xaui_miso                     : OUT t_mem_miso;
+
+    -- Serial I/O
+    xaui_tx_arr                   : OUT t_unb1_board_xaui_sl_2arr(g_nof_macs-1 DOWNTO 0);  
+    xaui_rx_arr                   : IN  t_unb1_board_xaui_sl_2arr(g_nof_macs-1 DOWNTO 0);
+
+    mdio_rst                      : OUT STD_LOGIC;
+    mdio_mdc_arr                  : OUT STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0);  
+    mdio_mdat_in_arr              : IN  STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0) := (OTHERS=>'0');
+    mdio_mdat_oen_arr             : OUT STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0)
+  );
+END node_unb1_tr_10GbE;
+
+
+ARCHITECTURE str OF node_unb1_tr_10GbE IS
+
+--CONSTANT c_block_len            : NATURAL := 180; -- = 1440 user bytes. Including packetizing: 1508 bytes.
+  CONSTANT c_block_len            : NATURAL := 1118;-- = 8944 user bytes. Including packetizing: 9012 bytes.
+
+  SIGNAL tr_rst                   : STD_LOGIC;
+
+  SIGNAL i_xaui_tx_arr            : t_xaui_arr(g_nof_macs-1 DOWNTO 0);
+  SIGNAL i_xaui_rx_arr            : t_xaui_arr(g_nof_macs-1 DOWNTO 0);
+
+  SIGNAL diagnostics_snk_in_arr   : t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0); 
+  SIGNAL diagnostics_snk_out_arr  : t_dp_siso_arr(g_nof_macs-1 DOWNTO 0);
+
+  SIGNAL diagnostics_src_out_arr  : t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0);
+  SIGNAL diagnostics_src_in_arr   : t_dp_siso_arr(g_nof_macs-1 DOWNTO 0);
+
+BEGIN
+
+  -- Wire together different types
+  gen_wires: FOR i IN 0 TO g_nof_macs-1 GENERATE
+    xaui_tx_arr(i) <= i_xaui_tx_arr(i);
+    i_xaui_rx_arr(i) <= xaui_rx_arr(i);
+  END GENERATE;
+
+  u_async : ENTITY common_lib.common_async
+  GENERIC MAP (
+    g_rst_level => '1'
+  )
+  PORT MAP (
+    rst  => dp_rst,
+    clk  => dp_clk,
+    din  => dp_rst,
+    dout => tr_rst
+  );
+  
+  u_mms_diagnostics: ENTITY diagnostics_lib.mms_diagnostics
+  GENERIC MAP(
+    g_data_w       => c_xgmii_data_w,
+    g_block_len    => c_block_len,
+    g_nof_streams  => g_nof_macs,
+    g_separate_clk => FALSE
+  )                      
+  PORT MAP (       
+    mm_rst          => mm_rst,  
+    mm_clk          => mm_clk,
+
+    st_rst          => dp_rst,
+    st_clk          => dp_clk,
+
+    mm_mosi         => reg_diagnostics_mosi, 
+    mm_miso         => reg_diagnostics_miso,
+
+    src_out_arr     => diagnostics_src_out_arr,
+    src_in_arr      => diagnostics_src_in_arr,
+
+    snk_out_arr     => diagnostics_snk_out_arr,
+    snk_in_arr      => diagnostics_snk_in_arr
+  );
+
+  u_tr_10GbE: ENTITY tr_10GbE_lib.tr_10GbE
+  GENERIC MAP(
+    g_sim           => g_sim,
+    g_sim_level     => g_sim_level,
+    g_nof_macs      => g_nof_macs,
+    g_use_mdio      => g_use_mdio,
+    g_mdio_epcs_dis => g_mdio_epcs_dis,
+    g_lpbk_sosi     => g_lpbk_sosi,   
+    g_lpbk_xgmii    => g_lpbk_xgmii,  
+    g_lpbk_xaui     => g_lpbk_xaui,
+    g_use_hdr_ram   => TRUE,
+    g_hdr_ram_init_file => "../../../src/hex/default_eth_header.hex",
+    g_hdr_release_at_init => '1', --Release default header at init so packets are sent after powerup without manual settings
+    g_pkt_len       => 1130 -- 1130 64b words = 9040B (enough for jumbo frame)
+  )                      
+  PORT MAP (       
+    mm_rst              => mm_rst,  
+    mm_clk              => mm_clk,
+
+    tr_clk              => tr_clk,
+
+    cal_rec_clk         => cal_rec_clk,
+
+    dp_rst              => dp_rst,
+    dp_clk              => dp_clk,
+
+    reg_mac_mosi        => reg_mac_mosi, 
+    reg_mac_miso        => reg_mac_miso,
+
+    xaui_mosi           => xaui_mosi,
+    xaui_miso           => xaui_miso,
+
+    reg_hdr_insert_mosi => reg_hdr_insert_mosi,
+    ram_hdr_insert_mosi => ram_hdr_insert_mosi,
+                                               
+    ram_hdr_remove_mosi => ram_hdr_remove_mosi,
+    ram_hdr_remove_miso => ram_hdr_remove_miso,
+
+    src_out_arr         => diagnostics_snk_in_arr,
+    src_in_arr          => diagnostics_snk_out_arr,
+
+    snk_out_arr         => diagnostics_src_in_arr,
+    snk_in_arr          => diagnostics_src_out_arr,
+
+    xaui_tx_out_arr     => i_xaui_tx_arr, 
+    xaui_rx_in_arr      => i_xaui_rx_arr,  
+
+    -- Serial IO for Arria
+    tx_serial_data        => OPEN,
+    rx_serial_data        => (OTHERS => '0'),
+
+    mdio_rst            => mdio_rst,
+    mdio_mdc_arr        => mdio_mdc_arr,
+    mdio_mdat_in_arr    => mdio_mdat_in_arr,
+    mdio_mdat_oen_arr   => mdio_mdat_oen_arr
+  );
+
+END str;