From faf239df77d9c698b3cabcc091cc221b7fa3f2c0 Mon Sep 17 00:00:00 2001
From: Leon Hiemstra <hiemstra@astron.nl>
Date: Wed, 1 Oct 2014 15:22:37 +0000
Subject: [PATCH] svn cp from unb_tr_10GbE. Converted to RadioHDL. Tested in
frontnode.
---
.../designs/unb1_tr_10GbE/hdllib.cfg | 32 +
.../unb1_tr_10GbE/quartus/sopc_tr_10GbE.sopc | 1147 +++++++++++++++++
.../quartus/unb1_tr_10GbE_pins.tcl | 87 ++
.../src/hex/default_eth_header.hex | 9 +
.../src/python/gen_hex_file_dp_ram_from_mm.py | 153 +++
.../src/vhdl/node_unb1_tr_10GbE.vhd | 197 +++
.../unb1_tr_10GbE/src/vhdl/unb1_tr_10GbE.vhd | 514 ++++++++
7 files changed, 2139 insertions(+)
create mode 100644 boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg
create mode 100644 boards/uniboard1/designs/unb1_tr_10GbE/quartus/sopc_tr_10GbE.sopc
create mode 100644 boards/uniboard1/designs/unb1_tr_10GbE/quartus/unb1_tr_10GbE_pins.tcl
create mode 100644 boards/uniboard1/designs/unb1_tr_10GbE/src/hex/default_eth_header.hex
create mode 100644 boards/uniboard1/designs/unb1_tr_10GbE/src/python/gen_hex_file_dp_ram_from_mm.py
create mode 100644 boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/node_unb1_tr_10GbE.vhd
create mode 100644 boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/unb1_tr_10GbE.vhd
diff --git a/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg b/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg
new file mode 100644
index 0000000000..c765618b55
--- /dev/null
+++ b/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg
@@ -0,0 +1,32 @@
+hdl_lib_name = unb1_tr_10GbE
+hdl_library_clause_name = unb1_tr_10GbE_lib
+hdl_lib_uses = common mm i2c unb1_board dp eth tr_xaui tr_10GbE mdio diagnostics
+hdl_lib_technology = ip_stratixiv
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+synth_files =
+ $HDL_BUILD_DIR/quartus/unb1_tr_10GbE/sopc_tr_10GbE.vhd
+ src/vhdl/node_unb1_tr_10GbE.vhd
+ src/vhdl/unb1_tr_10GbE.vhd
+
+test_bench_files =
+
+synth_top_level_entity =
+synth_revision =
+
+synth_copy_files =
+ quartus/sopc_tr_10GbE.sopc .
+
+quartus_qsf_files =
+ $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+
+quartus_tcl_files =
+ quartus/unb1_tr_10GbE_pins.tcl
+
+quartus_vhdl_files =
+
+quartus_qip_files =
+ $HDL_BUILD_DIR/quartus/unb1_tr_10GbE/sopc_tr_10GbE.qip
+
diff --git a/boards/uniboard1/designs/unb1_tr_10GbE/quartus/sopc_tr_10GbE.sopc b/boards/uniboard1/designs/unb1_tr_10GbE/quartus/sopc_tr_10GbE.sopc
new file mode 100644
index 0000000000..c6b6a095df
--- /dev/null
+++ b/boards/uniboard1/designs/unb1_tr_10GbE/quartus/sopc_tr_10GbE.sopc
@@ -0,0 +1,1147 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="sopc_tr_10GbE">
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element altpll_0
+ {
+ datum _sortIndex
+ {
+ value = "1";
+ type = "int";
+ }
+ }
+ element jtag_uart_0.avalon_jtag_slave
+ {
+ datum baseAddress
+ {
+ value = "1120";
+ type = "long";
+ }
+ }
+ element avs_eth_0
+ {
+ datum _sortIndex
+ {
+ value = "9";
+ type = "int";
+ }
+ }
+ element altpll_0.c0
+ {
+ datum _clockDomain
+ {
+ value = "mm_clk";
+ type = "String";
+ }
+ }
+ element altpll_0.c1
+ {
+ datum _clockDomain
+ {
+ value = "cal_reconf_clk";
+ type = "String";
+ }
+ }
+ element altpll_0.c2
+ {
+ datum _clockDomain
+ {
+ value = "tse_clk";
+ type = "String";
+ }
+ }
+ element altpll_0.c3
+ {
+ datum _clockDomain
+ {
+ value = "dp_clk";
+ type = "String";
+ }
+ }
+ element clk_0
+ {
+ datum _sortIndex
+ {
+ value = "5";
+ type = "int";
+ }
+ }
+ element cpu_0
+ {
+ datum _sortIndex
+ {
+ value = "4";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{}";
+ type = "String";
+ }
+ }
+ element cpu_0.jtag_debug_module
+ {
+ datum baseAddress
+ {
+ value = "14336";
+ type = "long";
+ }
+ }
+ element jtag_uart_0
+ {
+ datum _sortIndex
+ {
+ value = "3";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{}";
+ type = "String";
+ }
+ }
+ element reg_dp_ram_from_mm.mem
+ {
+ datum baseAddress
+ {
+ value = "1024";
+ type = "long";
+ }
+ }
+ element reg_wdi.mem
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "12288";
+ type = "long";
+ }
+ }
+ element ram_dp_ram_to_mm.mem
+ {
+ datum baseAddress
+ {
+ value = "768";
+ type = "long";
+ }
+ }
+ element rom_system_info.mem
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "4096";
+ type = "long";
+ }
+ }
+ element reg_tr_xaui.mem
+ {
+ datum baseAddress
+ {
+ value = "16384";
+ type = "long";
+ }
+ }
+ element pio_system_info.mem
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "0";
+ type = "long";
+ }
+ }
+ element ram_dp_ram_from_mm.mem
+ {
+ datum baseAddress
+ {
+ value = "512";
+ type = "long";
+ }
+ }
+ element reg_diagnostics.mem
+ {
+ datum baseAddress
+ {
+ value = "256";
+ type = "long";
+ }
+ }
+ element reg_unb_sens.mem
+ {
+ datum baseAddress
+ {
+ value = "224";
+ type = "long";
+ }
+ }
+ element reg_tr_10GbE.mem
+ {
+ datum baseAddress
+ {
+ value = "262144";
+ type = "long";
+ }
+ }
+ element avs_eth_0.mms_ram
+ {
+ datum baseAddress
+ {
+ value = "24576";
+ type = "long";
+ }
+ }
+ element avs_eth_0.mms_reg
+ {
+ datum baseAddress
+ {
+ value = "128";
+ type = "long";
+ }
+ }
+ element avs_eth_0.mms_tse
+ {
+ datum baseAddress
+ {
+ value = "8192";
+ type = "long";
+ }
+ }
+ element onchip_memory2_0
+ {
+ datum _sortIndex
+ {
+ value = "2";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{output_language=VHDL, output_directory=D:\\svnroot\\UniBoard_FP7\\UniBoard\\trunk\\Firmware\\designs\\unb_tr_nonbonded\\build\\synth\\quartus}";
+ type = "String";
+ }
+ }
+ element pio_debug_wave
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+ element pio_pps
+ {
+ datum _sortIndex
+ {
+ value = "14";
+ type = "int";
+ }
+ }
+ element pio_system_info
+ {
+ datum _sortIndex
+ {
+ value = "12";
+ type = "int";
+ }
+ }
+ element pio_wdi
+ {
+ datum _sortIndex
+ {
+ value = "6";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{}";
+ type = "String";
+ }
+ }
+ element altpll_0.pll_slave
+ {
+ datum _lockedAddress
+ {
+ value = "0";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "1056";
+ type = "long";
+ }
+ }
+ element ram_dp_ram_from_mm
+ {
+ datum _sortIndex
+ {
+ value = "17";
+ type = "int";
+ }
+ }
+ element ram_dp_ram_to_mm
+ {
+ datum _sortIndex
+ {
+ value = "18";
+ type = "int";
+ }
+ }
+ element reg_diagnostics
+ {
+ datum _sortIndex
+ {
+ value = "7";
+ type = "int";
+ }
+ }
+ element reg_dp_ram_from_mm
+ {
+ datum _sortIndex
+ {
+ value = "16";
+ type = "int";
+ }
+ }
+ element reg_tr_10GbE
+ {
+ datum _sortIndex
+ {
+ value = "15";
+ type = "int";
+ }
+ }
+ element reg_tr_xaui
+ {
+ datum _sortIndex
+ {
+ value = "19";
+ type = "int";
+ }
+ }
+ element reg_unb_sens
+ {
+ datum _sortIndex
+ {
+ value = "11";
+ type = "int";
+ }
+ }
+ element reg_wdi
+ {
+ datum _sortIndex
+ {
+ value = "13";
+ type = "int";
+ }
+ }
+ element rom_system_info
+ {
+ datum _sortIndex
+ {
+ value = "10";
+ type = "int";
+ }
+ }
+ element pio_wdi.s1
+ {
+ datum baseAddress
+ {
+ value = "1088";
+ type = "long";
+ }
+ }
+ element pio_pps.s1
+ {
+ datum baseAddress
+ {
+ value = "1104";
+ type = "long";
+ }
+ }
+ element timer_0.s1
+ {
+ datum baseAddress
+ {
+ value = "192";
+ type = "long";
+ }
+ }
+ element onchip_memory2_0.s1
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "131072";
+ type = "long";
+ }
+ }
+ element pio_debug_wave.s1
+ {
+ datum baseAddress
+ {
+ value = "1072";
+ type = "long";
+ }
+ }
+ element sopc_tr_10GbE
+ {
+ }
+ element timer_0
+ {
+ datum _sortIndex
+ {
+ value = "8";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="EP4SGX230KF40C2" />
+ <parameter name="deviceFamily" value="STRATIXIV" />
+ <parameter name="deviceSpeedGrade" value="" />
+ <parameter name="fabricMode" value="SOPC" />
+ <parameter name="generateLegacySim" value="true" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="true" />
+ <parameter name="hdlLanguage" value="VHDL" />
+ <parameter name="maxAdditionalLatency" value="0" />
+ <parameter name="projectName" value="unb1_tr_10GbE.qpf" />
+ <parameter name="sopcBorderPoints" value="true" />
+ <parameter name="systemHash" value="-55271282509" />
+ <parameter name="timeStamp" value="1411635296347" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <module kind="clock_source" version="11.1" enabled="1" name="clk_0">
+ <parameter name="clockFrequency" value="25000000" />
+ <parameter name="clockFrequencyKnown" value="true" />
+ <parameter name="inputClockFrequency" value="0" />
+ <parameter name="resetSynchronousEdges" value="NONE" />
+ </module>
+ <module kind="altera_nios2" version="11.1" enabled="1" name="cpu_0">
+ <parameter name="userDefinedSettings" value="" />
+ <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster0MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
+ <parameter name="setting_showUnpublishedSettings" value="false" />
+ <parameter name="setting_showInternalSettings" value="false" />
+ <parameter name="setting_shadowRegisterSets" value="0" />
+ <parameter name="setting_preciseSlaveAccessErrorException" value="false" />
+ <parameter name="setting_preciseIllegalMemAccessException" value="false" />
+ <parameter name="setting_preciseDivisionErrorException" value="false" />
+ <parameter name="setting_performanceCounter" value="false" />
+ <parameter name="setting_perfCounterWidth" value="_32" />
+ <parameter name="setting_interruptControllerType" value="Internal" />
+ <parameter name="setting_illegalMemAccessDetection" value="false" />
+ <parameter name="setting_illegalInstructionsTrap" value="false" />
+ <parameter name="setting_fullWaveformSignals" value="false" />
+ <parameter name="setting_extraExceptionInfo" value="false" />
+ <parameter name="setting_exportPCB" value="false" />
+ <parameter name="setting_debugSimGen" value="false" />
+ <parameter name="setting_clearXBitsLDNonBypass" value="true" />
+ <parameter name="setting_branchPredictionType" value="Automatic" />
+ <parameter name="setting_bit31BypassDCache" value="true" />
+ <parameter name="setting_bigEndian" value="false" />
+ <parameter name="setting_bhtPtrSz" value="_8" />
+ <parameter name="setting_bhtIndexPcOnly" value="false" />
+ <parameter name="setting_avalonDebugPortPresent" value="false" />
+ <parameter name="setting_alwaysEncrypt" value="true" />
+ <parameter name="setting_allowFullAddressRange" value="false" />
+ <parameter name="setting_activateTrace" value="true" />
+ <parameter name="setting_activateTestEndChecker" value="false" />
+ <parameter name="setting_activateMonitors" value="true" />
+ <parameter name="setting_activateModelChecker" value="false" />
+ <parameter name="setting_HDLSimCachesCleared" value="true" />
+ <parameter name="setting_HBreakTest" value="false" />
+ <parameter name="resetSlave" value="onchip_memory2_0.s1" />
+ <parameter name="resetOffset" value="0" />
+ <parameter name="muldiv_multiplierType" value="DSPBlock" />
+ <parameter name="muldiv_divider" value="false" />
+ <parameter name="mpu_useLimit" value="false" />
+ <parameter name="mpu_numOfInstRegion" value="8" />
+ <parameter name="mpu_numOfDataRegion" value="8" />
+ <parameter name="mpu_minInstRegionSize" value="_12" />
+ <parameter name="mpu_minDataRegionSize" value="_12" />
+ <parameter name="mpu_enabled" value="false" />
+ <parameter name="mmu_uitlbNumEntries" value="_4" />
+ <parameter name="mmu_udtlbNumEntries" value="_6" />
+ <parameter name="mmu_tlbPtrSz" value="_7" />
+ <parameter name="mmu_tlbNumWays" value="_16" />
+ <parameter name="mmu_processIDNumBits" value="_8" />
+ <parameter name="mmu_enabled" value="false" />
+ <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
+ <parameter name="mmu_TLBMissExcSlave" value="" />
+ <parameter name="mmu_TLBMissExcOffset" value="0" />
+ <parameter name="manuallyAssignCpuID" value="false" />
+ <parameter name="internalIrqMaskSystemInfo" value="7" />
+ <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
+ <parameter name="instAddrWidth" value="18" />
+ <parameter name="impl" value="Small" />
+ <parameter name="icache_size" value="_4096" />
+ <parameter name="icache_ramBlockType" value="Automatic" />
+ <parameter name="icache_numTCIM" value="_0" />
+ <parameter name="icache_burstType" value="None" />
+ <parameter name="exceptionSlave" value="onchip_memory2_0.s1" />
+ <parameter name="exceptionOffset" value="32" />
+ <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 1 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 1 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 1 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+ <parameter name="deviceFamilyName" value="Stratix IV" />
+ <parameter name="debug_triggerArming" value="true" />
+ <parameter name="debug_level" value="Level1" />
+ <parameter name="debug_jtagInstanceID" value="0" />
+ <parameter name="debug_embeddedPLL" value="true" />
+ <parameter name="debug_debugReqSignals" value="false" />
+ <parameter name="debug_assignJtagInstanceID" value="false" />
+ <parameter name="debug_OCIOnchipTrace" value="_128" />
+ <parameter name="dcache_size" value="_2048" />
+ <parameter name="dcache_ramBlockType" value="Automatic" />
+ <parameter name="dcache_omitDataMaster" value="false" />
+ <parameter name="dcache_numTCDM" value="_0" />
+ <parameter name="dcache_lineSize" value="_32" />
+ <parameter name="dcache_bursts" value="false" />
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='timer_0.s1' start='0xC0' end='0xE0' /><slave name='reg_unb_sens.mem' start='0xE0' end='0x100' /><slave name='reg_diagnostics.mem' start='0x100' end='0x200' /><slave name='ram_dp_ram_from_mm.mem' start='0x200' end='0x300' /><slave name='ram_dp_ram_to_mm.mem' start='0x300' end='0x400' /><slave name='reg_dp_ram_from_mm.mem' start='0x400' end='0x420' /><slave name='altpll_0.pll_slave' start='0x420' end='0x430' /><slave name='pio_debug_wave.s1' start='0x430' end='0x440' /><slave name='pio_wdi.s1' start='0x440' end='0x450' /><slave name='pio_pps.s1' start='0x450' end='0x460' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x460' end='0x468' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='reg_tr_xaui.mem' start='0x4000' end='0x6000' /><slave name='avs_eth_0.mms_ram' start='0x6000' end='0x7000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_tr_10GbE.mem' start='0x40000' end='0x60000' /></address-map>]]></parameter>
+ <parameter name="dataAddrWidth" value="19" />
+ <parameter name="customInstSlavesSystemInfo" value="<info/>" />
+ <parameter name="cpuReset" value="false" />
+ <parameter name="cpuID" value="0" />
+ <parameter name="clockFrequency" value="125000000" />
+ <parameter name="breakSlave">cpu_0.jtag_debug_module</parameter>
+ <parameter name="breakOffset" value="32" />
+ </module>
+ <module
+ kind="altera_avalon_onchip_memory2"
+ version="11.1"
+ enabled="1"
+ name="onchip_memory2_0">
+ <parameter name="allowInSystemMemoryContentEditor" value="false" />
+ <parameter name="autoInitializationFileName" value="onchip_memory2_0" />
+ <parameter name="blockType" value="M144K" />
+ <parameter name="dataWidth" value="32" />
+ <parameter name="deviceFamily" value="Stratix IV" />
+ <parameter name="dualPort" value="false" />
+ <parameter name="initMemContent" value="true" />
+ <parameter name="initializationFileName" value="onchip_memory2_0" />
+ <parameter name="instanceID" value="NONE" />
+ <parameter name="memorySize" value="131072" />
+ <parameter name="readDuringWriteMode" value="DONT_CARE" />
+ <parameter name="simAllowMRAMContentsFile" value="false" />
+ <parameter name="simMemInitOnlyFilename" value="0" />
+ <parameter name="singleClockOperation" value="false" />
+ <parameter name="slave1Latency" value="1" />
+ <parameter name="slave2Latency" value="1" />
+ <parameter name="useNonDefaultInitFile" value="false" />
+ <parameter name="useShallowMemBlocks" value="false" />
+ <parameter name="writable" value="true" />
+ </module>
+ <module
+ kind="altera_avalon_jtag_uart"
+ version="11.1"
+ enabled="1"
+ name="jtag_uart_0">
+ <parameter name="allowMultipleConnections" value="false" />
+ <parameter name="hubInstanceID" value="0" />
+ <parameter name="readBufferDepth" value="64" />
+ <parameter name="readIRQThreshold" value="8" />
+ <parameter name="simInputCharacterStream"><![CDATA[a
+q]]></parameter>
+ <parameter name="simInteractiveOptions">INTERACTIVE_ASCII_OUTPUT</parameter>
+ <parameter name="useRegistersForReadBuffer" value="false" />
+ <parameter name="useRegistersForWriteBuffer" value="false" />
+ <parameter name="useRelativePathForSimFile" value="false" />
+ <parameter name="writeBufferDepth" value="64" />
+ <parameter name="writeIRQThreshold" value="8" />
+ </module>
+ <module kind="altpll" version="11.1" enabled="1" name="altpll_0">
+ <parameter name="HIDDEN_CUSTOM_ELABORATION">altpll_avalon_elaboration</parameter>
+ <parameter name="HIDDEN_CUSTOM_POST_EDIT">altpll_avalon_post_edit</parameter>
+ <parameter name="INTENDED_DEVICE_FAMILY" value="Stratix IV" />
+ <parameter name="WIDTH_CLOCK" value="10" />
+ <parameter name="WIDTH_PHASECOUNTERSELECT" value="" />
+ <parameter name="PRIMARY_CLOCK" value="" />
+ <parameter name="INCLK0_INPUT_FREQUENCY" value="40000" />
+ <parameter name="INCLK1_INPUT_FREQUENCY" value="" />
+ <parameter name="OPERATION_MODE" value="NORMAL" />
+ <parameter name="PLL_TYPE" value="AUTO" />
+ <parameter name="QUALIFY_CONF_DONE" value="" />
+ <parameter name="COMPENSATE_CLOCK" value="CLK0" />
+ <parameter name="SCAN_CHAIN" value="" />
+ <parameter name="GATE_LOCK_SIGNAL" value="" />
+ <parameter name="GATE_LOCK_COUNTER" value="" />
+ <parameter name="LOCK_HIGH" value="" />
+ <parameter name="LOCK_LOW" value="" />
+ <parameter name="VALID_LOCK_MULTIPLIER" value="" />
+ <parameter name="INVALID_LOCK_MULTIPLIER" value="" />
+ <parameter name="SWITCH_OVER_ON_LOSSCLK" value="" />
+ <parameter name="SWITCH_OVER_ON_GATED_LOCK" value="" />
+ <parameter name="ENABLE_SWITCH_OVER_COUNTER" value="" />
+ <parameter name="SKIP_VCO" value="" />
+ <parameter name="SWITCH_OVER_COUNTER" value="" />
+ <parameter name="SWITCH_OVER_TYPE" value="" />
+ <parameter name="FEEDBACK_SOURCE" value="" />
+ <parameter name="BANDWIDTH" value="" />
+ <parameter name="BANDWIDTH_TYPE" value="AUTO" />
+ <parameter name="SPREAD_FREQUENCY" value="" />
+ <parameter name="DOWN_SPREAD" value="" />
+ <parameter name="SELF_RESET_ON_GATED_LOSS_LOCK" value="" />
+ <parameter name="SELF_RESET_ON_LOSS_LOCK" value="" />
+ <parameter name="CLK0_MULTIPLY_BY" value="5" />
+ <parameter name="CLK1_MULTIPLY_BY" value="8" />
+ <parameter name="CLK2_MULTIPLY_BY" value="5" />
+ <parameter name="CLK3_MULTIPLY_BY" value="8" />
+ <parameter name="CLK4_MULTIPLY_BY" value="" />
+ <parameter name="CLK5_MULTIPLY_BY" value="" />
+ <parameter name="CLK6_MULTIPLY_BY" value="" />
+ <parameter name="CLK7_MULTIPLY_BY" value="" />
+ <parameter name="CLK8_MULTIPLY_BY" value="" />
+ <parameter name="CLK9_MULTIPLY_BY" value="" />
+ <parameter name="EXTCLK0_MULTIPLY_BY" value="" />
+ <parameter name="EXTCLK1_MULTIPLY_BY" value="" />
+ <parameter name="EXTCLK2_MULTIPLY_BY" value="" />
+ <parameter name="EXTCLK3_MULTIPLY_BY" value="" />
+ <parameter name="CLK0_DIVIDE_BY" value="1" />
+ <parameter name="CLK1_DIVIDE_BY" value="5" />
+ <parameter name="CLK2_DIVIDE_BY" value="1" />
+ <parameter name="CLK3_DIVIDE_BY" value="1" />
+ <parameter name="CLK4_DIVIDE_BY" value="" />
+ <parameter name="CLK5_DIVIDE_BY" value="" />
+ <parameter name="CLK6_DIVIDE_BY" value="" />
+ <parameter name="CLK7_DIVIDE_BY" value="" />
+ <parameter name="CLK8_DIVIDE_BY" value="" />
+ <parameter name="CLK9_DIVIDE_BY" value="" />
+ <parameter name="EXTCLK0_DIVIDE_BY" value="" />
+ <parameter name="EXTCLK1_DIVIDE_BY" value="" />
+ <parameter name="EXTCLK2_DIVIDE_BY" value="" />
+ <parameter name="EXTCLK3_DIVIDE_BY" value="" />
+ <parameter name="CLK0_PHASE_SHIFT" value="0" />
+ <parameter name="CLK1_PHASE_SHIFT" value="0" />
+ <parameter name="CLK2_PHASE_SHIFT" value="0" />
+ <parameter name="CLK3_PHASE_SHIFT" value="0" />
+ <parameter name="CLK4_PHASE_SHIFT" value="" />
+ <parameter name="CLK5_PHASE_SHIFT" value="" />
+ <parameter name="CLK6_PHASE_SHIFT" value="" />
+ <parameter name="CLK7_PHASE_SHIFT" value="" />
+ <parameter name="CLK8_PHASE_SHIFT" value="" />
+ <parameter name="CLK9_PHASE_SHIFT" value="" />
+ <parameter name="EXTCLK0_PHASE_SHIFT" value="" />
+ <parameter name="EXTCLK1_PHASE_SHIFT" value="" />
+ <parameter name="EXTCLK2_PHASE_SHIFT" value="" />
+ <parameter name="EXTCLK3_PHASE_SHIFT" value="" />
+ <parameter name="CLK0_DUTY_CYCLE" value="50" />
+ <parameter name="CLK1_DUTY_CYCLE" value="50" />
+ <parameter name="CLK2_DUTY_CYCLE" value="50" />
+ <parameter name="CLK3_DUTY_CYCLE" value="50" />
+ <parameter name="CLK4_DUTY_CYCLE" value="" />
+ <parameter name="CLK5_DUTY_CYCLE" value="" />
+ <parameter name="CLK6_DUTY_CYCLE" value="" />
+ <parameter name="CLK7_DUTY_CYCLE" value="" />
+ <parameter name="CLK8_DUTY_CYCLE" value="" />
+ <parameter name="CLK9_DUTY_CYCLE" value="" />
+ <parameter name="EXTCLK0_DUTY_CYCLE" value="" />
+ <parameter name="EXTCLK1_DUTY_CYCLE" value="" />
+ <parameter name="EXTCLK2_DUTY_CYCLE" value="" />
+ <parameter name="EXTCLK3_DUTY_CYCLE" value="" />
+ <parameter name="PORT_clkena0" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena1" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena2" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena3" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena4" value="PORT_UNUSED" />
+ <parameter name="PORT_clkena5" value="PORT_UNUSED" />
+ <parameter name="PORT_extclkena0" value="" />
+ <parameter name="PORT_extclkena1" value="" />
+ <parameter name="PORT_extclkena2" value="" />
+ <parameter name="PORT_extclkena3" value="" />
+ <parameter name="PORT_extclk0" value="" />
+ <parameter name="PORT_extclk1" value="" />
+ <parameter name="PORT_extclk2" value="" />
+ <parameter name="PORT_extclk3" value="" />
+ <parameter name="PORT_CLKBAD0" value="PORT_UNUSED" />
+ <parameter name="PORT_CLKBAD1" value="PORT_UNUSED" />
+ <parameter name="PORT_clk0" value="PORT_USED" />
+ <parameter name="PORT_clk1" value="PORT_USED" />
+ <parameter name="PORT_clk2" value="PORT_USED" />
+ <parameter name="PORT_clk3" value="PORT_USED" />
+ <parameter name="PORT_clk4" value="PORT_UNUSED" />
+ <parameter name="PORT_clk5" value="PORT_UNUSED" />
+ <parameter name="PORT_clk6" value="PORT_UNUSED" />
+ <parameter name="PORT_clk7" value="PORT_UNUSED" />
+ <parameter name="PORT_clk8" value="PORT_UNUSED" />
+ <parameter name="PORT_clk9" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANDATA" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANDATAOUT" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANDONE" value="PORT_UNUSED" />
+ <parameter name="PORT_SCLKOUT1" value="" />
+ <parameter name="PORT_SCLKOUT0" value="" />
+ <parameter name="PORT_ACTIVECLOCK" value="PORT_UNUSED" />
+ <parameter name="PORT_CLKLOSS" value="PORT_UNUSED" />
+ <parameter name="PORT_INCLK1" value="PORT_UNUSED" />
+ <parameter name="PORT_INCLK0" value="PORT_USED" />
+ <parameter name="PORT_FBIN" value="PORT_UNUSED" />
+ <parameter name="PORT_PLLENA" value="PORT_UNUSED" />
+ <parameter name="PORT_CLKSWITCH" value="PORT_UNUSED" />
+ <parameter name="PORT_ARESET" value="PORT_UNUSED" />
+ <parameter name="PORT_PFDENA" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANCLK" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANACLR" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANREAD" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANWRITE" value="PORT_UNUSED" />
+ <parameter name="PORT_ENABLE0" value="" />
+ <parameter name="PORT_ENABLE1" value="" />
+ <parameter name="PORT_LOCKED" value="PORT_USED" />
+ <parameter name="PORT_CONFIGUPDATE" value="PORT_UNUSED" />
+ <parameter name="PORT_FBOUT" value="PORT_UNUSED" />
+ <parameter name="PORT_PHASEDONE" value="PORT_UNUSED" />
+ <parameter name="PORT_PHASESTEP" value="PORT_UNUSED" />
+ <parameter name="PORT_PHASEUPDOWN" value="PORT_UNUSED" />
+ <parameter name="PORT_SCANCLKENA" value="PORT_UNUSED" />
+ <parameter name="PORT_PHASECOUNTERSELECT" value="PORT_UNUSED" />
+ <parameter name="PORT_VCOOVERRANGE" value="" />
+ <parameter name="PORT_VCOUNDERRANGE" value="" />
+ <parameter name="DPA_MULTIPLY_BY" value="" />
+ <parameter name="DPA_DIVIDE_BY" value="" />
+ <parameter name="DPA_DIVIDER" value="" />
+ <parameter name="VCO_MULTIPLY_BY" value="" />
+ <parameter name="VCO_DIVIDE_BY" value="" />
+ <parameter name="SCLKOUT0_PHASE_SHIFT" value="" />
+ <parameter name="SCLKOUT1_PHASE_SHIFT" value="" />
+ <parameter name="VCO_FREQUENCY_CONTROL" value="" />
+ <parameter name="VCO_PHASE_SHIFT_STEP" value="" />
+ <parameter name="USING_FBMIMICBIDIR_PORT" value="OFF" />
+ <parameter name="SCAN_CHAIN_MIF_FILE" value="" />
+ <parameter name="AVALON_USE_SEPARATE_SYSCLK" value="NO" />
+ <parameter name="HIDDEN_CONSTANTS">CT#CLK2_DIVIDE_BY 1 CT#PORT_clk9 PORT_UNUSED CT#PORT_clk8 PORT_UNUSED CT#PORT_clk7 PORT_UNUSED CT#PORT_clk6 PORT_UNUSED CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_USED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 5 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#CLK3_DUTY_CYCLE 50 CT#CLK3_DIVIDE_BY 1 CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#CLK3_PHASE_SHIFT 0 CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 10 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 8 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 40000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_FBOUT PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 0 CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 5 CT#INTENDED_DEVICE_FAMILY {Stratix IV} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 5 CT#CLK3_MULTIPLY_BY 8 CT#USING_FBMIMICBIDIR_PORT OFF CT#PORT_LOCKED PORT_USED</parameter>
+ <parameter name="HIDDEN_PRIVATES">PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 25.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#OUTPUT_FREQ_UNIT3 MHz PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK3 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#LVDS_PHASE_SHIFT_UNIT3 deg PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#OUTPUT_FREQ_MODE3 1 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ3 200.00000000 PT#OUTPUT_FREQ2 125.00000000 PT#OUTPUT_FREQ1 40.00000000 PT#OUTPUT_FREQ0 125.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT3 0.00000000 PT#PHASE_SHIFT2 0.00000000 PT#DIV_FACTOR3 1 PT#PHASE_SHIFT1 0.00000000 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 1 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE3 200.000000 PT#EFF_OUTPUT_FREQ_VALUE2 125.000000 PT#EFF_OUTPUT_FREQ_VALUE1 40.000000 PT#EFF_OUTPUT_FREQ_VALUE0 125.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK3 1 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT3 deg PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR3 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE3 50.00000000 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {Stratix IV} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1256297171721465.mif PT#ACTIVECLK_CHECK 0</parameter>
+ <parameter name="HIDDEN_USED_PORTS">UP#locked used UP#c3 used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used</parameter>
+ <parameter name="HIDDEN_IS_NUMERIC">IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK3_DIVIDE_BY 1 IN#CLK1_MULTIPLY_BY 1 IN#CLK3_DUTY_CYCLE 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR3 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#CLK3_MULTIPLY_BY 1 IN#MULT_FACTOR3 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1</parameter>
+ <parameter name="HIDDEN_MF_PORTS">MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1</parameter>
+ <parameter name="HIDDEN_IF_PORTS">IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#c3 {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0}</parameter>
+ <parameter name="HIDDEN_IS_FIRST_EDIT" value="0" />
+ <parameter name="AUTO_INCLK_INTERFACE_CLOCK_RATE" value="25000000" />
+ <parameter name="AUTO_DEVICE_FAMILY" value="Stratix IV" />
+ </module>
+ <module
+ kind="altera_avalon_pio"
+ version="11.1"
+ enabled="1"
+ name="pio_debug_wave">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="125000000" />
+ <parameter name="direction" value="Output" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="32" />
+ </module>
+ <module kind="altera_avalon_pio" version="11.1" enabled="1" name="pio_wdi">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="125000000" />
+ <parameter name="direction" value="Output" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="1" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_diagnostics">
+ <parameter name="g_adr_w" value="6" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module kind="altera_avalon_timer" version="11.1" enabled="1" name="timer_0">
+ <parameter name="alwaysRun" value="true" />
+ <parameter name="counterSize" value="32" />
+ <parameter name="fixedPeriod" value="true" />
+ <parameter name="period" value="1" />
+ <parameter name="periodUnits" value="MSEC" />
+ <parameter name="resetOutput" value="false" />
+ <parameter name="snapshot" value="false" />
+ <parameter name="systemFrequency" value="125000000" />
+ <parameter name="timeoutPulseOutput" value="false" />
+ <parameter name="timerPreset">SIMPLE_PERIODIC_INTERRUPT</parameter>
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="rom_system_info">
+ <parameter name="g_adr_w" value="10" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_unb_sens">
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="pio_system_info">
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_wdi">
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module kind="altera_avalon_pio" version="11.1" enabled="1" name="pio_pps">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="125000000" />
+ <parameter name="direction" value="Input" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="32" />
+ </module>
+ <module
+ kind="avs_common_mm_readlatency0"
+ version="1.0"
+ enabled="1"
+ name="reg_tr_10GbE">
+ <parameter name="g_adr_w" value="15" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_dp_ram_from_mm">
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="ram_dp_ram_from_mm">
+ <parameter name="g_adr_w" value="6" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="ram_dp_ram_to_mm">
+ <parameter name="g_adr_w" value="6" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module
+ kind="avs_common_mm_readlatency0"
+ version="1.0"
+ enabled="1"
+ name="reg_tr_xaui">
+ <parameter name="g_adr_w" value="11" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
+ </module>
+ <module kind="avs2_eth_coe" version="1.0" enabled="1" name="avs_eth_0">
+ <parameter name="AUTO_MM_CLOCK_RATE" value="125000000" />
+ </module>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.instruction_master"
+ end="cpu_0.jtag_debug_module">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3800" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="cpu_0.jtag_debug_module">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3800" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.instruction_master"
+ end="onchip_memory2_0.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00020000" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="onchip_memory2_0.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00020000" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="jtag_uart_0.avalon_jtag_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0460" />
+ </connection>
+ <connection
+ kind="interrupt"
+ version="11.1"
+ start="cpu_0.d_irq"
+ end="jtag_uart_0.irq">
+ <parameter name="irqNumber" value="0" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="altpll_0.pll_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0420" />
+ </connection>
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="cpu_0.clk" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="onchip_memory2_0.clk1" />
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="jtag_uart_0.clk" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_0.clk"
+ end="altpll_0.inclk_interface" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="pio_debug_wave.clk" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="pio_debug_wave.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0430" />
+ </connection>
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="pio_wdi.clk" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="pio_wdi.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0440" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="reg_diagnostics.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_diagnostics.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0100" />
+ </connection>
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="timer_0.clk" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="timer_0.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00c0" />
+ </connection>
+ <connection kind="interrupt" version="11.1" start="cpu_0.d_irq" end="timer_0.irq">
+ <parameter name="irqNumber" value="1" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="rom_system_info.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="rom_system_info.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x1000" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="reg_unb_sens.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_unb_sens.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00e0" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="pio_system_info.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="pio_system_info.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0000" />
+ </connection>
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="reg_wdi.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_wdi.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3000" />
+ </connection>
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="pio_pps.clk" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="pio_pps.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0450" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="reg_tr_10GbE.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_tr_10GbE.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00040000" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="reg_dp_ram_from_mm.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_dp_ram_from_mm.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0400" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="ram_dp_ram_from_mm.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="ram_dp_ram_from_mm.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0200" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="ram_dp_ram_to_mm.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="ram_dp_ram_to_mm.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0300" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="altpll_0.c0"
+ end="reg_tr_xaui.system" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_tr_xaui.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x4000" />
+ </connection>
+ <connection kind="clock" version="11.1" start="altpll_0.c0" end="avs_eth_0.mm" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="avs_eth_0.mms_tse">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x2000" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="avs_eth_0.mms_reg">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0080" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="avs_eth_0.mms_ram">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x6000" />
+ </connection>
+ <connection
+ kind="interrupt"
+ version="11.1"
+ start="cpu_0.d_irq"
+ end="avs_eth_0.interrupt">
+ <parameter name="irqNumber" value="2" />
+ </connection>
+</system>
diff --git a/boards/uniboard1/designs/unb1_tr_10GbE/quartus/unb1_tr_10GbE_pins.tcl b/boards/uniboard1/designs/unb1_tr_10GbE/quartus/unb1_tr_10GbE_pins.tcl
new file mode 100644
index 0000000000..3f1e6461e1
--- /dev/null
+++ b/boards/uniboard1/designs/unb1_tr_10GbE/quartus/unb1_tr_10GbE_pins.tcl
@@ -0,0 +1,87 @@
+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_general_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_other_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
+# -- Front Interface (10GbE)
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/FRONT_NODE_tr_cntrl_pins.tcl
+
+set_location_assignment PIN_AA2 -to SA_CLK
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SA_CLK
+
+set_location_assignment PIN_M4 -to SI_FN_0_TX[0]
+set_location_assignment PIN_K4 -to SI_FN_0_TX[1]
+set_location_assignment PIN_D4 -to SI_FN_0_TX[2]
+set_location_assignment PIN_B4 -to SI_FN_0_TX[3]
+set_location_assignment PIN_N2 -to SI_FN_0_RX[0]
+set_location_assignment PIN_L2 -to SI_FN_0_RX[1]
+set_location_assignment PIN_E2 -to SI_FN_0_RX[2]
+set_location_assignment PIN_C2 -to SI_FN_0_RX[3]
+
+set_location_assignment PIN_AD4 -to SI_FN_1_TX[0]
+set_location_assignment PIN_AB4 -to SI_FN_1_TX[1]
+set_location_assignment PIN_T4 -to SI_FN_1_TX[2]
+set_location_assignment PIN_P4 -to SI_FN_1_TX[3]
+set_location_assignment PIN_AE2 -to SI_FN_1_RX[0]
+set_location_assignment PIN_AC2 -to SI_FN_1_RX[1]
+set_location_assignment PIN_U2 -to SI_FN_1_RX[2]
+set_location_assignment PIN_R2 -to SI_FN_1_RX[3]
+
+set_location_assignment PIN_AT4 -to SI_FN_2_TX[0]
+set_location_assignment PIN_AP4 -to SI_FN_2_TX[1]
+set_location_assignment PIN_AH4 -to SI_FN_2_TX[2]
+set_location_assignment PIN_AF4 -to SI_FN_2_TX[3]
+set_location_assignment PIN_AU2 -to SI_FN_2_RX[0]
+set_location_assignment PIN_AR2 -to SI_FN_2_RX[1]
+set_location_assignment PIN_AJ2 -to SI_FN_2_RX[2]
+set_location_assignment PIN_AG2 -to SI_FN_2_RX[3]
+
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_0_TX[0]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_0_TX[1]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_0_TX[2]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_0_TX[3]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_0_RX[0]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_0_RX[1]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_0_RX[2]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_0_RX[3]
+
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_1_TX[0]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_1_TX[1]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_1_TX[2]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_1_TX[3]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_1_RX[0]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_1_RX[1]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_1_RX[2]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_1_RX[3]
+
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_2_TX[0]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_2_TX[1]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_2_TX[2]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_2_TX[3]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_2_RX[0]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_2_RX[1]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_2_RX[2]
+set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_2_RX[3]
+
+
+
diff --git a/boards/uniboard1/designs/unb1_tr_10GbE/src/hex/default_eth_header.hex b/boards/uniboard1/designs/unb1_tr_10GbE/src/hex/default_eth_header.hex
new file mode 100644
index 0000000000..80b6a9bc0f
--- /dev/null
+++ b/boards/uniboard1/designs/unb1_tr_10GbE/src/hex/default_eth_header.hex
@@ -0,0 +1,9 @@
+:0800000000074306C7000022BF
+:0800010086080000080045001C
+:080002002322000040007F11E1
+:08000300BA530A6300010A0A66
+:080004000A0A0FA00FA0230E51
+:080005000000000000000000F3
+:080006000000000000000000F2
+:080007000000000000000000F1
+:00000001FF
diff --git a/boards/uniboard1/designs/unb1_tr_10GbE/src/python/gen_hex_file_dp_ram_from_mm.py b/boards/uniboard1/designs/unb1_tr_10GbE/src/python/gen_hex_file_dp_ram_from_mm.py
new file mode 100644
index 0000000000..02ccd9781e
--- /dev/null
+++ b/boards/uniboard1/designs/unb1_tr_10GbE/src/python/gen_hex_file_dp_ram_from_mm.py
@@ -0,0 +1,153 @@
+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+from common import *
+from eth import ip_hdr_checksum
+from mem_init_file import list_to_hex
+
+# Purpose:
+# . Generate a HEX file with a default header for the RAM in tr_10GbE.vhd
+# Description:
+# . In unb_tr_10GbE, each diagnostics data block is packetized using the
+# header in the RAM.
+# . The HEX file generated here makes up the initial RAM contents.
+# . The RAM contents can be changed during run-time using
+# $UPE/peripherals/pi_dp_ram_from_mm.py.
+
+###############################################################################
+# Constants
+###############################################################################
+
+FILENAME = "../hex/default_eth_header.hex"
+WORD_WIDTH = 64 # With of the 10GbE MAC's user interface
+NOF_HDR_WORDS = 8 # 512 bits = 64 bytes (c_nof_header_words in tr_10GbE.vhd)
+NOF_PAYLOAD_WORDS = 1118 # c_block_len in node_unb_tr_10GbE.vhd
+NOF_PAYLOAD_BYTES = NOF_PAYLOAD_WORDS * c_word_w / c_byte_w # 8944 bytes
+MEM_WIDTH = WORD_WIDTH
+MEM_DEPTH = NOF_HDR_WORDS
+
+# Header lengths in bytes
+ETH_HDR_LENGTH = 14
+IP_HDR_LENGTH = 20
+UDP_HDR_LENGTH = 8
+USR_HDR_LENGTH = 22
+TOT_HDR_LENGTH = ETH_HDR_LENGTH+IP_HDR_LENGTH+UDP_HDR_LENGTH+USR_HDR_LENGTH
+
+print 'Creating Ethernet header'
+
+###############################################################################
+# Ethernet header
+###############################################################################
+eth_dst_mac = 0x00074306C700 # capture5
+eth_src_mac = 0x002286080000
+eth_type = 0x0800
+
+eth_hdr_bytes = CommonBytes(eth_dst_mac, 6) & \
+ CommonBytes(eth_src_mac, 6) & \
+ CommonBytes(eth_type , 2)
+
+###############################################################################
+# IP header
+###############################################################################
+ip_version = 4
+ip_header_length = 5 # 5 32b words
+ip_services = 0
+ip_total_length = IP_HDR_LENGTH + UDP_HDR_LENGTH + USR_HDR_LENGTH+ \
+ NOF_PAYLOAD_BYTES
+print 'ip_total_length=',ip_total_length
+ip_total_length = 8994
+print 'ip_total_length=',ip_total_length
+
+ip_identification = 0
+ip_flags = 2
+ip_fragment_offset = 0
+ip_time_to_live = 127
+ip_protocol = 17
+ip_header_checksum = 0 # to be calculated
+ip_src_addr = 0x0a630001 # 10.99.0.1
+ip_dst_addr = 0x0a0a0a0a # 10.10.10.10 # capture5
+
+ip_hdr_bits = CommonBits(ip_version , 4) & \
+ CommonBits(ip_header_length , 4) & \
+ CommonBits(ip_services , 8) & \
+ CommonBits(ip_total_length , 16) & \
+ CommonBits(ip_identification , 16) & \
+ CommonBits(ip_flags , 3) & \
+ CommonBits(ip_fragment_offset , 13) & \
+ CommonBits(ip_time_to_live , 8) & \
+ CommonBits(ip_protocol , 8) & \
+ CommonBits(ip_header_checksum , 16) & \
+ CommonBits(ip_src_addr , 32) & \
+ CommonBits(ip_dst_addr , 32)
+
+ip_hdr_bytes = CommonBytes(ip_hdr_bits.data, IP_HDR_LENGTH)
+
+# Calculate and insert the IP header checksum
+calced_checksum = ip_hdr_checksum(ip_hdr_bytes)
+print 'Inserting IP header checksum:', calced_checksum, '=', hex(calced_checksum)
+ip_hdr_bytes[9:8] = calced_checksum
+
+###############################################################################
+# UDP header
+###############################################################################
+#udp_src_port = 0x89AB
+#udp_dst_port = 0xCDEF
+udp_src_port = 4000
+udp_dst_port = 4000
+udp_total_length = USR_HDR_LENGTH + NOF_PAYLOAD_BYTES
+udp_total_length = 8974
+udp_checksum = 0 # Zero is fine
+
+udp_hdr_bytes = CommonBytes(udp_src_port , 2) & \
+ CommonBytes(udp_dst_port , 2) & \
+ CommonBytes(udp_total_length, 2) & \
+ CommonBytes(udp_checksum , 2)
+
+###############################################################################
+# USR header
+###############################################################################
+usr_hdr = 0
+usr_hdr_bytes = CommonBytes(usr_hdr, USR_HDR_LENGTH)
+
+###############################################################################
+# Total header
+###############################################################################
+tot_hdr_bytes = eth_hdr_bytes & ip_hdr_bytes & udp_hdr_bytes & usr_hdr_bytes
+
+###############################################################################
+# Convert header bytes to 64b word list
+# . The LS word of the RAM is released first. We want the MS part of the header
+# to be released into the MAC first, so we must fill the 64b word list in
+# reverse.
+###############################################################################
+tot_hdr_words = CommonWords64(tot_hdr_bytes.data, NOF_HDR_WORDS)
+
+word_list = []
+for w in reversed(range(NOF_HDR_WORDS)):
+ word_list.append(tot_hdr_words[w])
+ print 'w=',w,' data=',hex(tot_hdr_words[w])
+
+###############################################################################
+# Generate the HEX file
+###############################################################################
+print 'Generating hex file:', FILENAME
+list_to_hex(word_list, FILENAME, MEM_WIDTH, MEM_DEPTH)
+print 'Done.'
diff --git a/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/node_unb1_tr_10GbE.vhd b/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/node_unb1_tr_10GbE.vhd
new file mode 100644
index 0000000000..b0f0e81d1e
--- /dev/null
+++ b/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/node_unb1_tr_10GbE.vhd
@@ -0,0 +1,197 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2013
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb1_board_lib, dp_lib, tr_nonbonded_lib, tr_xaui_lib, diagnostics_lib, tr_10GbE_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE tr_xaui_lib.tr_xaui_pkg.ALL;
+
+ENTITY node_unb1_tr_10GbE IS
+ GENERIC (
+ g_sim : BOOLEAN;
+ g_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model
+ g_nof_macs : NATURAL;
+ g_use_mdio : BOOLEAN;
+ g_mdio_epcs_dis : BOOLEAN := FALSE; -- TRUE disables EPCS on init; e.g. to target a 10GbE card in PC that does not support it
+ g_lpbk_sosi : BOOLEAN := FALSE; -- i/o pins <-> )( <-> tr_xaui <-> )( <-> tr_10GbE <-> )( <-> user
+ g_lpbk_xgmii : BOOLEAN := FALSE; -- ^^ ^^ ^^
+ g_lpbk_xaui : BOOLEAN := FALSE -- g_lpbk_xaui| g_lpbk_xgmii| g_lpbk_sosi|
+ );
+ PORT (
+ -- System
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+
+ dp_rst : IN STD_LOGIC;
+ dp_clk : IN STD_LOGIC;
+
+ tr_clk : IN STD_LOGIC;
+ cal_rec_clk : IN STD_LOGIC;
+
+ -- MM registers
+ reg_diagnostics_mosi : IN t_mem_mosi;
+ reg_diagnostics_miso : OUT t_mem_miso;
+
+ reg_hdr_insert_mosi : IN t_mem_mosi;
+ ram_hdr_insert_mosi : IN t_mem_mosi;
+
+ ram_hdr_remove_mosi : IN t_mem_mosi;
+ ram_hdr_remove_miso : OUT t_mem_miso;
+
+ reg_mac_mosi : IN t_mem_mosi;
+ reg_mac_miso : OUT t_mem_miso;
+
+ xaui_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ xaui_miso : OUT t_mem_miso;
+
+ -- Serial I/O
+ xaui_tx_arr : OUT t_unb1_board_xaui_sl_2arr(g_nof_macs-1 DOWNTO 0);
+ xaui_rx_arr : IN t_unb1_board_xaui_sl_2arr(g_nof_macs-1 DOWNTO 0);
+
+ mdio_rst : OUT STD_LOGIC;
+ mdio_mdc_arr : OUT STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0);
+ mdio_mdat_in_arr : IN STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0) := (OTHERS=>'0');
+ mdio_mdat_oen_arr : OUT STD_LOGIC_VECTOR(g_nof_macs-1 DOWNTO 0)
+ );
+END node_unb1_tr_10GbE;
+
+
+ARCHITECTURE str OF node_unb1_tr_10GbE IS
+
+--CONSTANT c_block_len : NATURAL := 180; -- = 1440 user bytes. Including packetizing: 1508 bytes.
+ CONSTANT c_block_len : NATURAL := 1118;-- = 8944 user bytes. Including packetizing: 9012 bytes.
+
+ SIGNAL tr_rst : STD_LOGIC;
+
+ SIGNAL i_xaui_tx_arr : t_xaui_arr(g_nof_macs-1 DOWNTO 0);
+ SIGNAL i_xaui_rx_arr : t_xaui_arr(g_nof_macs-1 DOWNTO 0);
+
+ SIGNAL diagnostics_snk_in_arr : t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0);
+ SIGNAL diagnostics_snk_out_arr : t_dp_siso_arr(g_nof_macs-1 DOWNTO 0);
+
+ SIGNAL diagnostics_src_out_arr : t_dp_sosi_arr(g_nof_macs-1 DOWNTO 0);
+ SIGNAL diagnostics_src_in_arr : t_dp_siso_arr(g_nof_macs-1 DOWNTO 0);
+
+BEGIN
+
+ -- Wire together different types
+ gen_wires: FOR i IN 0 TO g_nof_macs-1 GENERATE
+ xaui_tx_arr(i) <= i_xaui_tx_arr(i);
+ i_xaui_rx_arr(i) <= xaui_rx_arr(i);
+ END GENERATE;
+
+ u_async : ENTITY common_lib.common_async
+ GENERIC MAP (
+ g_rst_level => '1'
+ )
+ PORT MAP (
+ rst => dp_rst,
+ clk => dp_clk,
+ din => dp_rst,
+ dout => tr_rst
+ );
+
+ u_mms_diagnostics: ENTITY diagnostics_lib.mms_diagnostics
+ GENERIC MAP(
+ g_data_w => c_xgmii_data_w,
+ g_block_len => c_block_len,
+ g_nof_streams => g_nof_macs,
+ g_separate_clk => FALSE
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ st_rst => dp_rst,
+ st_clk => dp_clk,
+
+ mm_mosi => reg_diagnostics_mosi,
+ mm_miso => reg_diagnostics_miso,
+
+ src_out_arr => diagnostics_src_out_arr,
+ src_in_arr => diagnostics_src_in_arr,
+
+ snk_out_arr => diagnostics_snk_out_arr,
+ snk_in_arr => diagnostics_snk_in_arr
+ );
+
+ u_tr_10GbE: ENTITY tr_10GbE_lib.tr_10GbE
+ GENERIC MAP(
+ g_sim => g_sim,
+ g_sim_level => g_sim_level,
+ g_nof_macs => g_nof_macs,
+ g_use_mdio => g_use_mdio,
+ g_mdio_epcs_dis => g_mdio_epcs_dis,
+ g_lpbk_sosi => g_lpbk_sosi,
+ g_lpbk_xgmii => g_lpbk_xgmii,
+ g_lpbk_xaui => g_lpbk_xaui,
+ g_use_hdr_ram => TRUE,
+ g_hdr_ram_init_file => "../../../src/hex/default_eth_header.hex",
+ g_hdr_release_at_init => '1', --Release default header at init so packets are sent after powerup without manual settings
+ g_pkt_len => 1130 -- 1130 64b words = 9040B (enough for jumbo frame)
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ tr_clk => tr_clk,
+
+ cal_rec_clk => cal_rec_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ reg_mac_mosi => reg_mac_mosi,
+ reg_mac_miso => reg_mac_miso,
+
+ xaui_mosi => xaui_mosi,
+ xaui_miso => xaui_miso,
+
+ reg_hdr_insert_mosi => reg_hdr_insert_mosi,
+ ram_hdr_insert_mosi => ram_hdr_insert_mosi,
+
+ ram_hdr_remove_mosi => ram_hdr_remove_mosi,
+ ram_hdr_remove_miso => ram_hdr_remove_miso,
+
+ src_out_arr => diagnostics_snk_in_arr,
+ src_in_arr => diagnostics_snk_out_arr,
+
+ snk_out_arr => diagnostics_src_in_arr,
+ snk_in_arr => diagnostics_src_out_arr,
+
+ xaui_tx_out_arr => i_xaui_tx_arr,
+ xaui_rx_in_arr => i_xaui_rx_arr,
+
+ -- Serial IO for Arria
+ tx_serial_data => OPEN,
+ rx_serial_data => (OTHERS => '0'),
+
+ mdio_rst => mdio_rst,
+ mdio_mdc_arr => mdio_mdc_arr,
+ mdio_mdat_in_arr => mdio_mdat_in_arr,
+ mdio_mdat_oen_arr => mdio_mdat_oen_arr
+ );
+
+END str;
diff --git a/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/unb1_tr_10GbE.vhd b/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/unb1_tr_10GbE.vhd
new file mode 100644
index 0000000000..08acc118ad
--- /dev/null
+++ b/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/unb1_tr_10GbE.vhd
@@ -0,0 +1,514 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2013
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb1_board_lib, mm_lib, eth_lib, tr_xaui_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_field_pkg.ALL;
+USE common_lib.common_network_total_header_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+USE eth_lib.eth_pkg.ALL;
+USE tr_xaui_lib.tr_xaui_pkg.ALL;
+
+-- /------------------------------------------------------------------------------------------------------------------\
+-- | Revision (g_design_name) | c_use_front | c_use_back | c_use_pc_target | c_lpbk_sosi | c_lpbk_xgmii | c_lpbk_xaui |
+-- |-----------------------------------------------------|-----------------| ------------|--------------|-------------|
+-- | fn_tr_10GbE | TRUE | FALSE | FALSE | FALSE | FALSE | FALSE |
+-- | fn_tr_10GbE_pc | TRUE | FALSE | TRUE | FALSE | FALSE | FALSE |
+-- | fn_tr_10GbE_lpbk_sosi | TRUE | FALSE | FALSE | TRUE | FALSE | FALSE |
+-- | fn_tr_10GbE_lpbk_xgmii | TRUE | FALSE | FALSE | FALSE | TRUE | FALSE |
+-- | fn_tr_10GbE_lpbk_xaui | TRUE | FALSE | FALSE | FALSE | FALSE | TRUE |
+-- | bn_tr_10GbE | FALSE | TRUE | FALSE | FALSE | FALSE | FALSE |
+-- | bn_tr_10GbE_lpbk_sosi | FALSE | TRUE | FALSE | TRUE | FALSE | FALSE |
+-- | bn_tr_10GbE_lpbk_xgmii | FALSE | TRUE | FALSE | FALSE | TRUE | FALSE |
+-- | bn_tr_10GbE_lpbk_xaui | FALSE | TRUE | FALSE | FALSE | FALSE | TRUE |
+-- \------------------------------------------------------------------------------------------------------------------/
+
+ENTITY unb1_tr_10GbE IS
+ GENERIC (
+ g_design_name : STRING := "unb1_tr_10GbE"; -- set by QSF
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_stamp_svn : NATURAL := 0 -- SVN revision -- set by QSF
+ );
+ PORT (
+ -- GENERAL
+-- CLK : IN STD_LOGIC; -- System Clock - not used as the SOPC generates dp_clk.
+ PPS : IN STD_LOGIC;
+ WDI : OUT STD_LOGIC;
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
+
+ -- I2C Interface to Sensors
+ sens_sc : INOUT STD_LOGIC;
+ sens_sd : INOUT STD_LOGIC;
+
+ -- 1GbE Control Interface
+ ETH_clk : IN STD_LOGIC;
+ ETH_SGIN : IN STD_LOGIC;
+ ETH_SGOUT : OUT STD_LOGIC;
+
+ -- Transceiver clocks
+ SA_CLK : IN STD_LOGIC; -- SerDes Clock BN-BI / SI_FN
+
+ -- Serial I/O
+ SI_FN_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_1_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+
+ SI_FN_0_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0); -- (0 = LASI; 1=MDC; 2=MDIO)
+ SI_FN_1_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+ SI_FN_2_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+ SI_FN_3_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+ SI_FN_RSTN : OUT STD_LOGIC := '1'; -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
+ -- So we need to assign a '1' to it.
+ BN_BI_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ BN_BI_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ BN_BI_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ BN_BI_1_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ BN_BI_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ BN_BI_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ BN_BI_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ BN_BI_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0)
+ );
+END unb1_tr_10GbE;
+
+
+ARCHITECTURE str OF unb1_tr_10GbE IS
+
+ -- Firmware version x.y
+ CONSTANT c_fw_version : t_unb1_board_fw_version := (0, 2);
+
+ -- Revision controlled constants
+ CONSTANT c_use_front : BOOLEAN := TRUE; --g_design_name(1 TO 2)="fn";
+ CONSTANT c_use_back : BOOLEAN := FALSE; --g_design_name(1 TO 2)="bn";
+ CONSTANT c_use_pc_target : BOOLEAN := TRUE; --g_design_name(g_design_name'LENGTH-1 TO g_design_name'LENGTH)="pc" AND c_use_front;
+ CONSTANT c_lpbk_sosi : BOOLEAN := g_design_name(g_design_name'LENGTH-8 TO g_design_name'LENGTH)="lpbk_sosi";
+ CONSTANT c_lpbk_xgmii : BOOLEAN := g_design_name(g_design_name'LENGTH-9 TO g_design_name'LENGTH)="lpbk_xgmii";
+ CONSTANT c_lpbk_xaui : BOOLEAN := g_design_name(g_design_name'LENGTH-8 TO g_design_name'LENGTH)="lpbk_xaui";
+ CONSTANT c_use_phy : t_c_unb1_board_use_phy := (1, sel_a_b(c_use_front, 1, 0), 0, sel_a_b(c_use_back, 1, 0), 0, 0, 0, 1);
+
+ -- 10GbE MAC / XAUI related
+ CONSTANT c_nof_macs : NATURAL := 3;
+ CONSTANT c_nof_mdio : NATURAL := 4;
+
+ CONSTANT c_mac_mm_addr_w : NATURAL := 13;
+ CONSTANT c_reg_tr_10GbE_addr_w : NATURAL := ceil_log2(c_nof_macs* pow2(c_mac_mm_addr_w));
+
+ CONSTANT c_xaui_mosi_addr_w : NATURAL := 9; --2^9 = range of 512 addresses
+ CONSTANT c_max_nof_xaui_inst : NATURAL := 4;
+ CONSTANT c_reg_tr_xaui_addr_w : NATURAL := ceil_log2(c_max_nof_xaui_inst * pow2(c_xaui_mosi_addr_w)); -- 4* 512 = 2048 addresses -> 11 address bits.
+
+ CONSTANT c_dp_ram_mm_adr_w : NATURAL := ceil_log2(c_eth_nof_udp_ports * pow2(ceil_log2(c_network_total_header_32b_nof_words)));
+
+ CONSTANT c_dp_reg_mm_nof_words : NATURAL := 1;
+ CONSTANT c_dp_reg_mm_adr_w : NATURAL := ceil_log2(c_eth_nof_udp_ports * pow2(ceil_log2(c_dp_reg_mm_nof_words)));
+
+ -- System
+ SIGNAL xo_clk : STD_LOGIC;
+ SIGNAL xo_rst : STD_LOGIC;
+ SIGNAL xo_rst_n : STD_LOGIC;
+ SIGNAL mm_clk : STD_LOGIC;
+ SIGNAL mm_locked : STD_LOGIC;
+ SIGNAL mm_rst : STD_LOGIC;
+ SIGNAL dp_rst : STD_LOGIC;
+ SIGNAL dp_clk : STD_LOGIC;
+
+ -- PIOs
+ SIGNAL pout_wdi : STD_LOGIC;
+ SIGNAL pin_pps : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+
+ -- WDI override
+ SIGNAL reg_wdi_mosi : t_mem_mosi;
+ SIGNAL reg_wdi_miso : t_mem_miso;
+
+ -- UniBoard system info
+ SIGNAL reg_unb_system_info_mosi : t_mem_mosi;
+ SIGNAL reg_unb_system_info_miso : t_mem_miso;
+ SIGNAL rom_unb_system_info_mosi : t_mem_mosi;
+ SIGNAL rom_unb_system_info_miso : t_mem_miso;
+
+ -- UniBoard I2C sens
+ SIGNAL reg_unb_sens_mosi : t_mem_mosi;
+ SIGNAL reg_unb_sens_miso : t_mem_miso;
+
+ -- eth1g
+ SIGNAL eth1g_tse_clk : STD_LOGIC;
+ SIGNAL eth1g_mm_rst : STD_LOGIC;
+ SIGNAL eth1g_tse_mosi : t_mem_mosi;
+ SIGNAL eth1g_tse_miso : t_mem_miso;
+ SIGNAL eth1g_reg_mosi : t_mem_mosi;
+ SIGNAL eth1g_reg_miso : t_mem_miso;
+ SIGNAL eth1g_reg_interrupt : STD_LOGIC;
+ SIGNAL eth1g_ram_mosi : t_mem_mosi;
+ SIGNAL eth1g_ram_miso : t_mem_miso;
+
+ -- Serial I/O
+ SIGNAL xaui_tx_arr : t_unb1_board_xaui_sl_2arr(c_nof_macs-1 DOWNTO 0);
+ SIGNAL xaui_rx_arr : t_unb1_board_xaui_sl_2arr(c_nof_macs-1 DOWNTO 0);
+
+ -- Transceiver clocks
+ SIGNAL cal_rec_clk : STD_LOGIC;
+
+ -- MDIO
+ SIGNAL mdio_mdc_arr : STD_LOGIC_VECTOR(c_nof_macs-1 DOWNTO 0);
+ SIGNAL mdio_mdat_in_arr : STD_LOGIC_VECTOR(c_nof_macs-1 DOWNTO 0);
+ SIGNAL mdio_mdat_oen_arr : STD_LOGIC_VECTOR(c_nof_macs-1 DOWNTO 0);
+
+ -- Diagnostics
+ SIGNAL reg_diagnostics_mosi : t_mem_mosi;
+ SIGNAL reg_diagnostics_miso : t_mem_miso;
+
+ SIGNAL reg_tr_10GbE_mosi : t_mem_mosi;
+ SIGNAL reg_tr_10GbE_miso : t_mem_miso;
+
+ SIGNAL reg_tr_xaui_mosi : t_mem_mosi;
+ SIGNAL reg_tr_xaui_miso : t_mem_miso;
+
+ SIGNAL reg_dp_ram_from_mm_mosi : t_mem_mosi;
+ SIGNAL reg_dp_ram_from_mm_miso : t_mem_miso := c_mem_miso_rst;
+
+ SIGNAL ram_dp_ram_from_mm_mosi : t_mem_mosi;
+ SIGNAL ram_dp_ram_from_mm_miso : t_mem_miso := c_mem_miso_rst;
+
+ SIGNAL ram_dp_ram_to_mm_mosi : t_mem_mosi;
+ SIGNAL ram_dp_ram_to_mm_miso : t_mem_miso;
+
+BEGIN
+
+ -----------------------------------------------------------------------------
+ -- General control function
+ -----------------------------------------------------------------------------
+ u_ctrl : ENTITY unb1_board_lib.ctrl_unb1_board
+ GENERIC MAP (
+ -- General
+ g_design_name => g_design_name,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ -- Use PHY Interface
+ g_use_phy => c_use_phy,
+ -- Use SOPC generated dp_clk
+ g_dp_clk_use_pll => FALSE
+ )
+ PORT MAP (
+ -- System
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => OPEN,
+ dp_pps => OPEN,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+ pin_pps => pin_pps,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- General
+ CLK => '0', -- SOPC-generated 200MHz dp_clk is used.
+ PPS => PPS,
+ WDI => WDI,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
+
+ -----------------------------------------------------------------------------
+ -- SOPC
+ -----------------------------------------------------------------------------
+ u_sopc : ENTITY work.sopc_tr_10GbE
+ PORT MAP (
+ clk_0 => xo_clk,
+ reset_n => xo_rst_n,
+ mm_clk => mm_clk,
+ cal_reconf_clk => cal_rec_clk,
+ tse_clk => eth1g_tse_clk,
+ dp_clk => dp_clk,
+
+ -- the_altpll_0
+ locked_from_the_altpll_0 => mm_locked,
+ phasedone_from_the_altpll_0 => OPEN,
+ areset_to_the_altpll_0 => xo_rst,
+
+ -- the_avs_eth_0
+ coe_clk_export_from_the_avs_eth_0 => OPEN,
+ coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
+ coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
+ coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
+ coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
+ coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
+ coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
+ coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
+ coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
+ coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
+ coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
+ coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
+ coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
+ coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_unb_sens
+ coe_clk_export_from_the_reg_unb_sens => OPEN,
+ coe_reset_export_from_the_reg_unb_sens => OPEN,
+ coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0),
+ coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
+ coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
+ coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_diagnostics
+ coe_clk_export_from_the_reg_diagnostics => OPEN,
+ coe_reset_export_from_the_reg_diagnostics => OPEN,
+ coe_address_export_from_the_reg_diagnostics => reg_diagnostics_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diagnostics_adr_w-1 DOWNTO 0),
+ coe_read_export_from_the_reg_diagnostics => reg_diagnostics_mosi.rd,
+ coe_readdata_export_to_the_reg_diagnostics => reg_diagnostics_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_reg_diagnostics => reg_diagnostics_mosi.wr,
+ coe_writedata_export_from_the_reg_diagnostics => reg_diagnostics_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_pio_debug_wave
+ out_port_from_the_pio_debug_wave => OPEN,
+
+ -- the_pio_pps
+ in_port_to_the_pio_pps => pin_pps,
+
+ -- the_pio_system_info: actually an avs_common_mm instance
+ coe_clk_export_from_the_pio_system_info => OPEN,
+ coe_reset_export_from_the_pio_system_info => OPEN,
+ coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0),
+ coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_rom_system_info
+ coe_clk_export_from_the_rom_system_info => OPEN,
+ coe_reset_export_from_the_rom_system_info => OPEN,
+ coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb1_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
+ coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
+ coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
+ coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_pio_wdi
+ out_port_from_the_pio_wdi => pout_wdi,
+
+ -- the_reg_wdi
+ coe_clk_export_from_the_reg_wdi => OPEN,
+ coe_reset_export_from_the_reg_wdi => OPEN,
+ coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
+ coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
+ coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
+ coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_tr_10GbE
+ coe_clk_export_from_the_reg_tr_10GbE => OPEN,
+ coe_reset_export_from_the_reg_tr_10GbE => OPEN,
+ coe_address_export_from_the_reg_tr_10GbE => reg_tr_10GbE_mosi.address(c_reg_tr_10GbE_addr_w-1 DOWNTO 0),
+ coe_read_export_from_the_reg_tr_10GbE => reg_tr_10GbE_mosi.rd,
+ coe_readdata_export_to_the_reg_tr_10GbE => reg_tr_10GbE_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_waitrequest_export_to_the_reg_tr_10GbE => reg_tr_10GbE_miso.waitrequest,
+ coe_write_export_from_the_reg_tr_10GbE => reg_tr_10GbE_mosi.wr,
+ coe_writedata_export_from_the_reg_tr_10GbE => reg_tr_10GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_dp_ram_from_mm
+ coe_clk_export_from_the_reg_dp_ram_from_mm => OPEN,
+ coe_reset_export_from_the_reg_dp_ram_from_mm => OPEN,
+ coe_address_export_from_the_reg_dp_ram_from_mm => reg_dp_ram_from_mm_mosi.address(c_dp_reg_mm_adr_w-1 DOWNTO 0),
+ coe_read_export_from_the_reg_dp_ram_from_mm => reg_dp_ram_from_mm_mosi.rd,
+ coe_readdata_export_to_the_reg_dp_ram_from_mm => reg_dp_ram_from_mm_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_reg_dp_ram_from_mm => reg_dp_ram_from_mm_mosi.wr,
+ coe_writedata_export_from_the_reg_dp_ram_from_mm => reg_dp_ram_from_mm_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_ram_dp_ram_from_mm
+ coe_clk_export_from_the_ram_dp_ram_from_mm => OPEN,
+ coe_reset_export_from_the_ram_dp_ram_from_mm => OPEN,
+ coe_address_export_from_the_ram_dp_ram_from_mm => ram_dp_ram_from_mm_mosi.address(c_dp_ram_mm_adr_w-1 DOWNTO 0),
+ coe_read_export_from_the_ram_dp_ram_from_mm => ram_dp_ram_from_mm_mosi.rd,
+ coe_readdata_export_to_the_ram_dp_ram_from_mm => ram_dp_ram_from_mm_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_ram_dp_ram_from_mm => ram_dp_ram_from_mm_mosi.wr,
+ coe_writedata_export_from_the_ram_dp_ram_from_mm => ram_dp_ram_from_mm_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_ram_dp_ram_to_mm
+ coe_clk_export_from_the_ram_dp_ram_to_mm => OPEN,
+ coe_reset_export_from_the_ram_dp_ram_to_mm => OPEN,
+ coe_address_export_from_the_ram_dp_ram_to_mm => ram_dp_ram_to_mm_mosi.address(c_dp_ram_mm_adr_w-1 DOWNTO 0),
+ coe_read_export_from_the_ram_dp_ram_to_mm => ram_dp_ram_to_mm_mosi.rd,
+ coe_readdata_export_to_the_ram_dp_ram_to_mm => ram_dp_ram_to_mm_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_write_export_from_the_ram_dp_ram_to_mm => ram_dp_ram_to_mm_mosi.wr,
+ coe_writedata_export_from_the_ram_dp_ram_to_mm => ram_dp_ram_to_mm_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ -- the_reg_tr_xaui
+ coe_clk_export_from_the_reg_tr_xaui => OPEN,
+ coe_reset_export_from_the_reg_tr_xaui => OPEN,
+ coe_address_export_from_the_reg_tr_xaui => reg_tr_xaui_mosi.address(c_reg_tr_xaui_addr_w-1 DOWNTO 0),
+ coe_read_export_from_the_reg_tr_xaui => reg_tr_xaui_mosi.rd,
+ coe_readdata_export_to_the_reg_tr_xaui => reg_tr_xaui_miso.rddata(c_word_w-1 DOWNTO 0),
+ coe_waitrequest_export_to_the_reg_tr_xaui => reg_tr_xaui_miso.waitrequest,
+ coe_write_export_from_the_reg_tr_xaui => reg_tr_xaui_mosi.wr,
+ coe_writedata_export_from_the_reg_tr_xaui => reg_tr_xaui_mosi.wrdata(c_word_w-1 DOWNTO 0)
+ );
+
+ -----------------------------------------------------------------------------
+ -- Node function
+ -----------------------------------------------------------------------------
+ u_node : ENTITY work.node_unb1_tr_10GbE
+ GENERIC MAP (
+ g_sim => FALSE,
+ g_nof_macs => c_nof_macs,
+ g_use_mdio => c_use_front,
+ g_mdio_epcs_dis => c_use_pc_target,
+ g_lpbk_sosi => c_lpbk_sosi,
+ g_lpbk_xgmii => c_lpbk_xgmii,
+ g_lpbk_xaui => c_lpbk_xaui
+ )
+ PORT MAP (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ tr_clk => SA_clk,
+ cal_rec_clk => cal_rec_clk,
+
+ -- MM registers
+ reg_diagnostics_mosi => reg_diagnostics_mosi,
+ reg_diagnostics_miso => reg_diagnostics_miso,
+
+ reg_mac_mosi => reg_tr_10GbE_mosi,
+ reg_mac_miso => reg_tr_10GbE_miso,
+
+ xaui_mosi => reg_tr_xaui_mosi,
+ xaui_miso => reg_tr_xaui_miso,
+
+ reg_hdr_insert_mosi => reg_dp_ram_from_mm_mosi,
+ ram_hdr_insert_mosi => ram_dp_ram_from_mm_mosi,
+
+ ram_hdr_remove_mosi => ram_dp_ram_to_mm_mosi,
+ ram_hdr_remove_miso => ram_dp_ram_to_mm_miso,
+
+ -- Transceiver serial I/O
+ xaui_tx_arr => xaui_tx_arr,
+ xaui_rx_arr => xaui_rx_arr,
+
+ -- MDIO External clock and serial data.
+ mdio_rst => SI_FN_RSTN,
+ mdio_mdc_arr => mdio_mdc_arr,
+ mdio_mdat_in_arr => mdio_mdat_in_arr,
+ mdio_mdat_oen_arr => mdio_mdat_oen_arr
+ );
+
+ -----------------------------------------------------------------------------
+ -- I/O wiring
+ -----------------------------------------------------------------------------
+ gen_tr_front : IF c_use_front=TRUE GENERATE
+ u_front_io : ENTITY unb1_board_lib.unb1_board_front_io
+ GENERIC MAP (
+ g_nof_xaui => c_nof_macs
+ )
+ PORT MAP (
+ xaui_tx_arr => xaui_tx_arr,
+ xaui_rx_arr => xaui_rx_arr,
+
+ mdio_mdc_arr => mdio_mdc_arr,
+ mdio_mdat_in_arr => mdio_mdat_in_arr,
+ mdio_mdat_oen_arr => mdio_mdat_oen_arr,
+
+ -- Serial I/O
+ SI_FN_0_TX => SI_FN_0_TX,
+ SI_FN_0_RX => SI_FN_0_RX,
+ SI_FN_1_TX => SI_FN_1_TX,
+ SI_FN_1_RX => SI_FN_1_RX,
+ SI_FN_2_TX => SI_FN_2_TX,
+ SI_FN_2_RX => SI_FN_2_RX,
+
+ SI_FN_0_CNTRL => SI_FN_0_CNTRL,
+ SI_FN_1_CNTRL => SI_FN_1_CNTRL,
+ SI_FN_2_CNTRL => SI_FN_2_CNTRL,
+ SI_FN_3_CNTRL => SI_FN_3_CNTRL
+ );
+ END GENERATE;
+
+END str;
--
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