- merged generics into g_reorder_seq

- removed unused constants 

applications/unb1_reorder/src/vhdl/node_unb1_reorder.vhd

@@ -33,19 +33,13 @@ USE reorder_lib.reorder_pkg.ALL;
 
 ENTITY node_unb1_reorder IS
   GENERIC (
-    g_sim            : BOOLEAN      := TRUE; 
-    g_nof_MB         : NATURAL      := c_unb1_board_nof_ddr3; -- Fixed control infrastructure for 2 modules per FPGA
-    g_use_MB_I       : NATURAL      := 1;              -- 1: use MB_I  0: do not use
-    g_tech_ddr       : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
-    g_wr_chunksize   : POSITIVE     := 256;
-    g_rd_chunksize   : POSITIVE     := 16;
-    g_rd_nof_chunks  : POSITIVE     := 16;  
-    g_rd_interval    : POSITIVE     := 16;
-    g_gapsize        : NATURAL      := 0;
-    g_nof_blocks     : POSITIVE     := 32;
-    g_nof_streams    : POSITIVE     := 4;
-    g_in_dat_w       : POSITIVE     := 8;
-    g_ena_pre_transp : BOOLEAN      := TRUE
+    g_sim            : BOOLEAN       := TRUE; 
+    g_use_MB_I       : NATURAL       := 1;              -- 1: use MB_I  0: do not use
+    g_tech_ddr       : t_c_tech_ddr  := c_tech_ddr3_4g_800m_master;
+    g_nof_streams    : POSITIVE      := 4;
+    g_in_dat_w       : POSITIVE      := 8;
+    g_ena_pre_transp : BOOLEAN       := TRUE;
+    g_reorder_seq    : t_reorder_seq := c_reorder_seq
  );
 PORT (
     -- System
@@ -69,7 +63,7 @@ PORT (
     -- ST source         
     out_siso_arr          : IN  t_dp_siso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
     out_sosi_arr          : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
-
+    
     -- DDR3 transpose       
     ram_ss_ss_transp_mosi : IN  t_mem_mosi; 
     ram_ss_ss_transp_miso : OUT t_mem_miso; 
@@ -99,18 +93,6 @@ ARCHITECTURE str OF node_unb1_reorder IS
   CONSTANT c_rd_fifo_depth          : NATURAL  := 256;     -- >=16 AND >g_tech_ddr.maxburstsize, defined at DDR side of the FIFO. 
   CONSTANT c_rd_data_w              : NATURAL  := c_data_w;
     
-  CONSTANT c_wr_flush_mode          : STRING   := "VAL";  -- "VAL", "SOP", "SYN"
-  CONSTANT c_wr_flush_use_channel   : BOOLEAN  := FALSE;
-  CONSTANT c_wr_flush_start_channel : NATURAL  := 0;
-  CONSTANT c_wr_flush_nof_channels  : POSITIVE := 1;
-                                    
-  CONSTANT c_reorder_seq_conf       : t_reorder_seq := (g_wr_chunksize, 
-                                                        g_rd_chunksize, 
-                                                        g_rd_nof_chunks,  
-                                                        g_rd_interval,
-                                                        g_gapsize,      
-                                                        g_nof_blocks);   
-
   -- Signals to interface with the DDR conroller and memory model.
   SIGNAL ctlr_dvr_miso              : t_mem_ctlr_miso;   
   SIGNAL ctlr_dvr_mosi              : t_mem_ctlr_mosi;  
@@ -126,7 +108,7 @@ ARCHITECTURE str OF node_unb1_reorder IS
   
   SIGNAL ctlr_clk                   : STD_LOGIC;
   SIGNAL ctlr_rst                   : STD_LOGIC;
-
+  
 BEGIN
 
   ------------------------------------------------------------------------------
@@ -138,11 +120,11 @@ BEGIN
     g_sim            => g_sim,   
     g_nof_streams    => g_nof_streams,      
     g_in_dat_w       => g_in_dat_w, 
-    g_frame_size_in  => g_wr_chunksize,               
-    g_frame_size_out => g_wr_chunksize,
+    g_frame_size_in  => g_reorder_seq.wr_chunksize,               
+    g_frame_size_out => g_reorder_seq.wr_chunksize,
     g_use_complex    => c_use_complex,  
     g_ena_pre_transp => g_ena_pre_transp,                    
-    g_reorder_seq    => c_reorder_seq_conf
+    g_reorder_seq    => g_reorder_seq
   )                          
   PORT MAP (        
     mm_rst                => mm_rst, 
@@ -231,7 +213,7 @@ BEGIN
 
     term_ctrl_out => OPEN,
     term_ctrl_in  => OPEN,
-
+    
     phy_in        => MB_I_IN(0),
     phy_io        => MB_I_IO(0),  
     phy_ou        => MB_I_OU(0)