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Commit fd75040d authored by Pepping's avatar Pepping
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- Fixed wrong connection of dp_clk and dp_rst on node entity 

- Added record for transpose generics 
- Added reset signal for reference reset for DDR
- Added ppsh registermap to ctrl_unb1_board
parent caad923e
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applications/unb1_reorder/src/vhdl/unb1_reorder.vhd
+ 57
− 52
View file @ fd75040d
......@@ -42,7 +42,6 @@ ENTITY unb1_reorder IS
g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD)
g_stamp_time : NATURAL := 0; -- Time (HHMMSS)
g_stamp_svn : NATURAL := 0; -- SVN revision
g_nof_MB : NATURAL := c_unb1_board_nof_ddr3; -- Fixed control infrastructure for 2 modules per FPGA
g_use_MB_I : NATURAL := 1; -- 1: use MB_I 0: do not use
g_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
g_aux : t_c_unb1_board_aux := c_unb1_board_aux
......@@ -80,27 +79,31 @@ END unb1_reorder;
ARCHITECTURE str OF unb1_reorder IS
-- Constant definitions for ctrl_unb_common
CONSTANT c_design_name : STRING := "unb1_reorder";
CONSTANT c_design_note : STRING := "Reference Reorder";
CONSTANT c_fw_version : t_unb1_board_fw_version := (0, 3); -- firmware version x.y
CONSTANT c_use_phy : t_c_unb1_board_use_phy := (1, 0, 0, 0, 1, 0, 0, 1);
CONSTANT c_aux : t_c_unb1_board_aux := c_unb1_board_aux;
CONSTANT c_app_led_en : BOOLEAN := TRUE;
CONSTANT c_wr_chunksize : POSITIVE := 256;
CONSTANT c_wr_nof_chunks : POSITIVE := 1;
CONSTANT c_rd_chunksize : POSITIVE := 32;
CONSTANT c_rd_nof_chunks : POSITIVE := 8;
CONSTANT c_rd_interval : POSITIVE := 32;
CONSTANT c_gapsize : NATURAL := 0;
CONSTANT c_nof_blocks : POSITIVE := 32;
CONSTANT c_nof_streams : POSITIVE := 4;
CONSTANT c_in_dat_w : POSITIVE := 8;
CONSTANT c_ena_pre_transp : BOOLEAN := TRUE;
CONSTANT c_frame_size_in : NATURAL := 256;
CONSTANT c_blocksize : POSITIVE := c_wr_nof_chunks * c_wr_chunksize;
CONSTANT c_design_name : STRING := "unb1_reorder";
CONSTANT c_design_note : STRING := "Reference Reorder";
CONSTANT c_fw_version : t_unb1_board_fw_version := (0, 8); -- firmware version x.y
CONSTANT c_use_phy : t_c_unb1_board_use_phy := (1, 0, 0, 0, 1, 0, 0, 1);
CONSTANT c_aux : t_c_unb1_board_aux := c_unb1_board_aux;
CONSTANT c_app_led_en : BOOLEAN := TRUE;
CONSTANT c_wr_chunksize : POSITIVE := 256;
CONSTANT c_wr_nof_chunks : POSITIVE := 1;
CONSTANT c_rd_chunksize : POSITIVE := 32;
CONSTANT c_rd_nof_chunks : POSITIVE := 8;
CONSTANT c_rd_interval : POSITIVE := 32;
CONSTANT c_gapsize : NATURAL := 0;
CONSTANT c_nof_blocks : POSITIVE := 32;
CONSTANT c_nof_streams : POSITIVE := 4;
CONSTANT c_in_dat_w : POSITIVE := 8;
CONSTANT c_ena_pre_transp : BOOLEAN := TRUE;
CONSTANT c_frame_size_in : NATURAL := 256;
CONSTANT c_blocksize : POSITIVE := c_wr_nof_chunks * c_wr_chunksize;
CONSTANT c_reorder_seq_conf : t_reorder_seq := (c_wr_chunksize,
c_rd_chunksize,
c_rd_nof_chunks,
c_rd_interval,
c_gapsize,
c_nof_blocks);
-- Block generator
CONSTANT c_bg_block_size : NATURAL := c_blocksize * c_rd_chunksize;
CONSTANT c_bg_gapsize : NATURAL := 0;
......@@ -116,7 +119,7 @@ ARCHITECTURE str OF unb1_reorder IS
CONSTANT c_bg_buf_dat_w : POSITIVE := c_nof_complex*c_in_dat_w;
CONSTANT c_bg_buf_adr_w : POSITIVE := ceil_log2(c_bg_block_size);
CONSTANT c_bg_data_file_prefix : STRING := "UNUSED"; --"hex/tb_bg_dat";
CONSTANT c_bg_data_file_prefix : STRING := "hex/tb_bg_dat";
CONSTANT c_bg_data_file_index_arr : t_nat_natural_arr := array_init(0, 128, 1);
......@@ -139,7 +142,8 @@ ARCHITECTURE str OF unb1_reorder IS
SIGNAL dp_rst : STD_LOGIC;
SIGNAL dp_clk : STD_LOGIC;
SIGNAL dp_pps : STD_LOGIC;
SIGNAL dp_pps : STD_LOGIC;
SIGNAL ddr_ref_rst : STD_LOGIC;
SIGNAL this_chip_id : STD_LOGIC_VECTOR(c_unb1_board_nof_chip_w-1 DOWNTO 0); -- [2:0], so range 0-3 for FN and range 4-7 BN
......@@ -203,9 +207,6 @@ ARCHITECTURE str OF unb1_reorder IS
SIGNAL reg_unb_sens_mosi : t_mem_mosi;
SIGNAL reg_unb_sens_miso : t_mem_miso;
SIGNAL reg_ddr3_mosi_arr : t_mem_mosi_arr(0 TO g_nof_MB-1);
SIGNAL reg_ddr3_miso_arr : t_mem_miso_arr(0 TO g_nof_MB-1);
SIGNAL reg_bsn_monitor_mosi : t_mem_mosi;
SIGNAL reg_bsn_monitor_miso : t_mem_miso;
......@@ -216,6 +217,8 @@ ARCHITECTURE str OF unb1_reorder IS
SIGNAL data_buf_snk_in_sosi_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
SIGNAL data_buf_snk_out_siso_arr : t_dp_siso_arr(c_nof_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
-- SIGNAL debug_out_arr : t_dp_sosi_arr(4 DOWNTO 0);
BEGIN
......@@ -273,6 +276,10 @@ BEGIN
reg_wdi_mosi => reg_wdi_mosi,
reg_wdi_miso => reg_wdi_miso,
-- . PPSH
reg_ppsh_mosi => reg_ppsh_mosi,
reg_ppsh_miso => reg_ppsh_miso,
-- system_info
reg_unb_system_info_mosi => reg_unb_system_info_mosi,
reg_unb_system_info_miso => reg_unb_system_info_miso,
......@@ -343,20 +350,14 @@ BEGIN
bsn_sosi_arr(0) <= block_gen_src_out_arr(0);
bsn_sosi_arr(1) <= data_buf_snk_in_sosi_arr(0);
u_mmm : ENTITY work.mmm_unb1_reorder
GENERIC MAP(
g_sim => g_sim,
g_sim_unb_nr => g_sim_unb_nr,
g_wr_chunksize => c_wr_chunksize,
g_wr_nof_chunks => c_wr_nof_chunks,
g_rd_chunksize => c_rd_chunksize,
g_rd_nof_chunks => c_rd_nof_chunks,
g_sim_node_nr => g_sim_node_nr,
g_nof_MB => g_nof_MB,
g_nof_streams => c_nof_streams,
g_frame_size_in => c_frame_size_in
g_sim => g_sim,
g_sim_unb_nr => g_sim_unb_nr,
g_sim_node_nr => g_sim_node_nr,
g_nof_streams => c_nof_streams,
g_reorder_seq => c_reorder_seq_conf
)
PORT MAP (
-- GENERAL
......@@ -425,21 +426,26 @@ BEGIN
reg_bsn_monitor_miso => reg_bsn_monitor_miso
);
u_areset_ddr_ref_rst : ENTITY common_lib.common_areset
GENERIC MAP(
g_rst_level => '1',
g_delay_len => 40
)
PORT MAP(
clk => CLK,
in_rst => '0',
out_rst => ddr_ref_rst
);
u_node : ENTITY work.node_unb1_reorder
GENERIC MAP(
g_sim => g_sim,
g_nof_MB => g_nof_MB,
g_use_MB_I => g_use_MB_I,
g_tech_ddr => g_tech_ddr,
g_wr_chunksize => c_wr_chunksize,
g_rd_chunksize => c_rd_chunksize,
g_rd_nof_chunks => c_rd_nof_chunks,
g_rd_interval => c_rd_interval,
g_gapsize => c_gapsize,
g_nof_blocks => c_nof_blocks,
g_nof_streams => c_nof_streams,
g_in_dat_w => c_in_dat_w,
g_ena_pre_transp => c_ena_pre_transp
g_ena_pre_transp => c_ena_pre_transp,
g_reorder_seq => c_reorder_seq_conf
)
PORT MAP(
-- System
......@@ -449,11 +455,11 @@ BEGIN
dp_clk => dp_clk,
ddr_ref_clk => CLK, -- Provide external 200 MHZ clk to DDR controller
ddr_ref_rst => dp_rst,
ddr_ref_rst => ddr_ref_rst,
-- Clock outputs
ddr_out_clk => dp_rst,
ddr_out_rst => dp_clk, -- dp_clk is generated by DDR controller
ddr_out_clk => dp_clk,
ddr_out_rst => dp_rst, -- dp_clk is generated by DDR controller
-- ST sinks
in_siso_arr => block_gen_src_in_arr,
......@@ -462,7 +468,7 @@ BEGIN
-- ST source
out_siso_arr => data_buf_snk_out_siso_arr,
out_sosi_arr => data_buf_snk_in_sosi_arr,
-- DDR3 transpose
ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
......@@ -473,7 +479,6 @@ BEGIN
MB_I_ou => MB_I_OU
);
-----------------------------------------------------------------------------
-- TX: Block generator
-----------------------------------------------------------------------------
......
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