Corrected IP source file name in commented section.

libraries/technology/ip_arria10/tse_sgmii_lvds/generate_ip.sh

@@ -44,7 +44,7 @@ qsys-generate ip_arria10_tse_sgmii_lvds.qsys \
               --allow-mixed-language-simulation
               
 # Also generate the testbench IP
-#qsys-generate ip_arria10_mac_10g.qsys \
+#qsys-generate ip_arria10_tse_sgmii_lvds.qsys \
 #              --synthesis=VHDL \
 #              --simulation=VHDL \
 #              --testbench=STANDARD \