The ip_arria10_tse_sgmii_lvds IP now simulates OK with tb_ip_arria10_tse_sgmii_lvds.vhd.

libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt

+README.txt for $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_lvds
+
+1) Porting
+2) IP component
+3) Compilation, simulation and verification
+4) Synthesis
+
+
+1) Porting
+
+The tse_sgmii_lvds IP was ported manually from Quartus v9.1 for Stratix IV  to Quartus 14.0a10 for Arria10 by creating it in Qsys using
+the same parameter settings.
+
+
+2) IP component
+
+The generated IP is not kept in SVN, only the Qsys source file:
+
+  ip_arria10_tse_sgmii_lvds.qsys
+
+Therefore first the IP needs to be generated using:
+
+  ./generate_ip.sh
+  
+
+3) Compilation, simulation and verification
+
+The genrated IP also contains a msim_setup.tcl file that was used to manually create:
+
+  compile_ip.tcl
+  
+This compile_ip.tcl is in the hdllib.cfg and gets compiled before the other code.
+The IP can be verified with the self checking test bench:
+
+  tb_ip_arria10_tse_sgmii_lvds.vhd
+  
+This test bench is functionally identical to tb_ip_stratixiv_tse_sgmii_lvds.vhd, but instead it instantiates the ip_arria10_tse_sgmii_lvds.vhd
+component as DUT.
+
+
+4) Synthesis
+
+No synthesis trials were done, because this will implicitely be done when the IP is used in a design. The QIP file:
+
+  generated/ip_arria10_tse_sgmii_lvds.qip
+
+is included in the hdllib.cfg and contains what is needed to synthesize the IP.

libraries/technology/ip_arria10/tse_sgmii_lvds/generate_ip.sh

+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014                                                        
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>           
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands                             
+#                                                                           
+# This program is free software: you can redistribute it and/or modify      
+# it under the terms of the GNU General Public License as published by      
+# the Free Software Foundation, either version 3 of the License, or         
+# (at your option) any later version.                                       
+#                                                                           
+# This program is distributed in the hope that it will be useful,           
+# but WITHOUT ANY WARRANTY; without even the implied warranty of            
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the             
+# GNU General Public License for more details.                              
+#                                                                           
+# You should have received a copy of the GNU General Public License         
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.     
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+#   Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+#   ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_tse_sgmii_lvds.qsys \
+              --synthesis=VHDL \
+              --simulation=VHDL \
+              --output-directory=generated \
+              --allow-mixed-language-simulation
+              
+# Also generate the testbench IP
+#qsys-generate ip_arria10_mac_10g.qsys \
+#              --synthesis=VHDL \
+#              --simulation=VHDL \
+#              --testbench=STANDARD \
+#              --testbench-simulation=VHDL \
+#              --output-directory=generated \
+#              --allow-mixed-language-simulation \
+#              --allow-mixed-language-testbench-simulation

libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg

+hdl_lib_name = ip_arria10_tse_sgmii_lvds
+hdl_library_clause_name = ip_arria10_tse_sgmii_lvds_lib
+hdl_lib_uses = common
+hdl_lib_technology = ip_arria10
+
+build_dir_sim = $HDL_BUILD_DIR
+build_dir_synth = $HDL_BUILD_DIR
+
+modelsim_compile_ip_files =
+    $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
+
+synth_files =
+    
+test_bench_files = 
+    tb_ip_arria10_tse_sgmii_lvds.vhd
+
+modelsim_search_libraries =
+    altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
+    altera     lpm     sgate     altera_mf     altera_lnsim     twentynm     twentynm_hssi     twentynm_hip
+
+quartus_qip_files =
+    generated/ip_arria10_tse_sgmii_lvds.qip