Moved build_dir_sim and build_dir_synth keys from local hdllib.cfg to central hdltool.cfg

applications/apertif/designs/apertif_unb1_correlator/hdllib.cfg

@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
 
 hdl_lib_technology = ip_stratixiv
 
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
 synth_top_level_entity =
 
 quartus_copy_files =

applications/apertif/designs/apertif_unb1_fn_beamformer/hdllib.cfg

@@ -3,9 +3,6 @@ hdl_library_clause_name = apertif_unb1_fn_beamformer_lib
 hdl_lib_uses_synth = common technology tech_mac_10g tr_10GbE mm i2c unb1_board bf apertif tech_ddr io_ddr
 hdl_lib_technology = ip_stratixiv
 
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
 modelsim_search_libraries =
     altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
     altera     lpm     sgate     altera_mf     altera_lnsim     stratixiv     stratixiv_hssi     stratixiv_pcie_hip

applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_base/hdllib.cfg

@@ -4,9 +4,6 @@ hdl_lib_uses_synth = unb1_board apertif_unb1_fn_beamformer tech_ddr_lib
 hdl_lib_technology = ip_stratixiv
 hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master ip_stratixiv_ddr3_uphy_4g_800_slave
 
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
 synth_top_level_entity =
 
 synth_files = apertif_unb1_fn_beamformer_base.vhd

applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_transpose/hdllib.cfg

@@ -4,9 +4,6 @@ hdl_lib_uses_synth = unb1_board apertif_unb1_fn_beamformer
 hdl_lib_technology = ip_stratixiv 
 hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave
 
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
 synth_top_level_entity =
 
 synth_files = apertif_unb1_fn_beamformer_trans.vhd

applications/apertif/libraries/apertif/hdllib.cfg

@@ -3,9 +3,6 @@ hdl_library_clause_name = apertif_lib
 hdl_lib_uses_synth = common
 hdl_lib_technology = ip_stratixiv
 
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
 synth_files =   
     src/vhdl/apertif_udp_offload_pkg.vhd
 

applications/compaan/designs/compaan_unb1_dp_offload/hdllib.cfg

@@ -3,9 +3,6 @@ hdl_library_clause_name = compaan_unb1_dp_offload_lib
 hdl_lib_uses_synth = common unb1_board dp eth tech_tse diag ipcore
 hdl_lib_technology = ip_stratixiv
 
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
 synth_files =
     $HDL_BUILD_DIR/quartus/compaan_unb1_dp_offload/sopc_compaan_unb1_dp_offload.vhd
     src/vhdl/pkg_signals.vhd

applications/compaan/libraries/hdllib.cfg

@@ -4,10 +4,6 @@ hdl_lib_uses_synth = common technology ip_arria10_fifo ip_stratixiv_fifo tech_fi
 
 hdl_lib_technology = ip_stratixiv
 
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library. 
 synth_files = 
     src/vhdl/compaandesign_com/common/common/1/hw_node_pkg.vhd
     src/vhdl/compaandesign_com/common/altera/1/fsl_v20.vhd

applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/altera/hdllib.cfg

@@ -3,10 +3,6 @@ hdl_library_clause_name = compaandesign_com_common_altera_1_lib
 hdl_lib_uses_synth = common dp 
 hdl_lib_technology = ip_stratixiv
 
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
 synth_files =
 	src/vhdl/fsl_v20.vhd
 

applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/common/hdllib.cfg

@@ -3,10 +3,6 @@ hdl_library_clause_name = compaandesign_com_common_common_1_lib
 hdl_lib_uses_synth = 
 hdl_lib_technology = ip_stratixiv
 
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
 synth_files =
 	src/vhdl/hw_node_pkg.vhd
 

applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/const_connector/hdllib.cfg

@@ -3,10 +3,6 @@ hdl_library_clause_name = compaandesign_com_common_const_connector_1_lib
 hdl_lib_uses_synth = 
 hdl_lib_technology = ip_stratixiv
 
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
 synth_files =
 	src/vhdl/const_connector.vhd
 

applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/extern_connector/hdllib.cfg

@@ -3,10 +3,6 @@ hdl_library_clause_name = compaandesign_com_common_extern_connector_1_lib
 hdl_lib_uses_synth = 
 hdl_lib_technology = ip_stratixiv
 
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
 synth_files =
 	src/vhdl/extern_connector.vhd
 

applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/fifo/hdllib.cfg

@@ -3,10 +3,6 @@ hdl_library_clause_name = compaandesign_com_common_fifo_1_lib
 hdl_lib_uses_synth = compaandesign_com_common_altera_1 
 hdl_lib_technology = ip_stratixiv
 
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
 synth_files =
 	src/vhdl/async_fifo_bram.vhd
 	src/vhdl/async_fifo.vhd

applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/hwnode/hdllib.cfg

@@ -3,10 +3,6 @@ hdl_library_clause_name = compaandesign_com_common_hwnode_1_lib
 hdl_lib_uses_synth = compaandesign_com_common_common_1 compaandesign_com_common_altera_1 
 hdl_lib_technology = ip_stratixiv
 
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
 synth_files =
 	src/vhdl/controller.vhd
 	src/vhdl/counter.vhd

applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/wire_connector/hdllib.cfg

@@ -3,10 +3,6 @@ hdl_library_clause_name = compaandesign_com_common_wire_connector_1_lib
 hdl_lib_uses_synth = 
 hdl_lib_technology = ip_stratixiv
 
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
 synth_files =
 	src/vhdl/wire_connector.vhd
 

applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/control_if/hdllib.cfg

@@ -3,10 +3,6 @@ hdl_library_clause_name = compaandesign_com_ipcore2RTL_control_if_1_lib
 hdl_lib_uses_synth = 
 hdl_lib_technology = ip_stratixiv
 
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
 synth_files =
 	src/vhdl/control_if.vhd
 

applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_1/hdllib.cfg

@@ -3,10 +3,6 @@ hdl_library_clause_name = compaandesign_com_ipcore2RTL_hwn_nd_1_1_lib
 hdl_lib_uses_synth = compaandesign_com_common_hwnode_1 compaandesign_com_common_common_1 
 hdl_lib_technology = ip_stratixiv
 
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
 synth_files =
 	src/vhdl/ipcore2RTL_hwn_nd_1_execution_unit.vhd
 	src/vhdl/ipcore2RTL_hwn_nd_1_eval_logic_rd.vhd

applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_2/hdllib.cfg

@@ -3,10 +3,6 @@ hdl_library_clause_name = compaandesign_com_ipcore2RTL_hwn_nd_2_1_lib
 hdl_lib_uses_synth = compaandesign_com_common_hwnode_1 compaandesign_com_common_common_1 
 hdl_lib_technology = ip_stratixiv
 
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
 synth_files =
 	src/vhdl/ipcore2RTL_hwn_nd_2_execution_unit.vhd
 	src/vhdl/ipcore2RTL_hwn_nd_2_eval_logic_rd.vhd

applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_3/hdllib.cfg

@@ -3,10 +3,6 @@ hdl_library_clause_name = compaandesign_com_ipcore2RTL_hwn_nd_3_1_lib
 hdl_lib_uses_synth = compaandesign_com_common_hwnode_1 compaandesign_com_common_common_1 
 hdl_lib_technology = ip_stratixiv
 
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
 synth_files =
 	src/vhdl/ipcore2RTL_hwn_nd_3_execution_unit.vhd
 	src/vhdl/ipcore2RTL_hwn_nd_3_eval_logic_rd.vhd

applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/register_rf/hdllib.cfg

@@ -3,10 +3,6 @@ hdl_library_clause_name = compaandesign_com_ipcore2RTL_register_rf_1_lib
 hdl_lib_uses_synth = 
 hdl_lib_technology = ip_stratixiv
 
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
 synth_files =
 	src/vhdl/register_rf.vhd
 

applications/compaan/libraries/ipcore_trace/astron/hdllib.cfg

@@ -4,10 +4,6 @@ hdl_library_clause_name = ipcore_lib
 hdl_lib_uses_synth = compaandesign_com_ipcore2RTL_hwn_nd_1_1 compaandesign_com_ipcore2RTL_hwn_nd_2_1 compaandesign_com_ipcore2RTL_register_rf_1 compaandesign_com_ipcore2RTL_hwn_nd_3_1 compaandesign_com_ipcore2RTL_control_if_1 compaandesign_com_common_altera_1 
 hdl_lib_technology = ip_stratixiv
 
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
 synth_files = 
 	src/vhdl/ipcore.vhd
 	src/vhdl/ipcore2RTL_control_if_ip_wrapper.vhd