diff --git a/applications/apertif/designs/apertif_unb1_correlator/hdllib.cfg b/applications/apertif/designs/apertif_unb1_correlator/hdllib.cfg
index c7b68ff1a6c3c25fedebb793ee23218fc40739e4..ee990784a3df315b66804b5a79719138d96e3ea7 100644
--- a/applications/apertif/designs/apertif_unb1_correlator/hdllib.cfg
+++ b/applications/apertif/designs/apertif_unb1_correlator/hdllib.cfg
@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
synth_top_level_entity =
quartus_copy_files =
diff --git a/applications/apertif/designs/apertif_unb1_fn_beamformer/hdllib.cfg b/applications/apertif/designs/apertif_unb1_fn_beamformer/hdllib.cfg
index d363993f7aa57a425aaaad1d94a04571f7bb4d58..24273044935fc8201464f9c746c759bfcc8f2386 100644
--- a/applications/apertif/designs/apertif_unb1_fn_beamformer/hdllib.cfg
+++ b/applications/apertif/designs/apertif_unb1_fn_beamformer/hdllib.cfg
@@ -3,9 +3,6 @@ hdl_library_clause_name = apertif_unb1_fn_beamformer_lib
hdl_lib_uses_synth = common technology tech_mac_10g tr_10GbE mm i2c unb1_board bf apertif tech_ddr io_ddr
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
modelsim_search_libraries =
altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip
diff --git a/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_base/hdllib.cfg b/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_base/hdllib.cfg
index 41a1c891f58a44cba042054c78a7ca6f581a0aaf..621e5bb964ee3f91f076630fa6a5918010c0b01f 100644
--- a/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_base/hdllib.cfg
+++ b/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_base/hdllib.cfg
@@ -4,9 +4,6 @@ hdl_lib_uses_synth = unb1_board apertif_unb1_fn_beamformer tech_ddr_lib
hdl_lib_technology = ip_stratixiv
hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_master ip_stratixiv_ddr3_uphy_4g_800_slave
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
synth_top_level_entity =
synth_files = apertif_unb1_fn_beamformer_base.vhd
diff --git a/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_transpose/hdllib.cfg b/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_transpose/hdllib.cfg
index 5cb22124210b5d5a07cfd2e2e63dd794fff00640..8eddc955625b1406bd5d54984bd947dd8aec861b 100644
--- a/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_transpose/hdllib.cfg
+++ b/applications/apertif/designs/apertif_unb1_fn_beamformer/revisions/apertif_unb1_fn_beamformer_transpose/hdllib.cfg
@@ -4,9 +4,6 @@ hdl_lib_uses_synth = unb1_board apertif_unb1_fn_beamformer
hdl_lib_technology = ip_stratixiv
hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
synth_top_level_entity =
synth_files = apertif_unb1_fn_beamformer_trans.vhd
diff --git a/applications/apertif/libraries/apertif/hdllib.cfg b/applications/apertif/libraries/apertif/hdllib.cfg
index 990a45d8e80f97c3664059befc5eb5554a51c315..1ebbb7bcda643df0b6efc6f62bb2d4426693f2a9 100644
--- a/applications/apertif/libraries/apertif/hdllib.cfg
+++ b/applications/apertif/libraries/apertif/hdllib.cfg
@@ -3,9 +3,6 @@ hdl_library_clause_name = apertif_lib
hdl_lib_uses_synth = common
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
synth_files =
src/vhdl/apertif_udp_offload_pkg.vhd
diff --git a/applications/compaan/designs/compaan_unb1_dp_offload/hdllib.cfg b/applications/compaan/designs/compaan_unb1_dp_offload/hdllib.cfg
index ec8604e7c2efdda9418755c811e620faa2f7bea9..a4addbe7fa329c0423028cf8069cf01326b6983e 100644
--- a/applications/compaan/designs/compaan_unb1_dp_offload/hdllib.cfg
+++ b/applications/compaan/designs/compaan_unb1_dp_offload/hdllib.cfg
@@ -3,9 +3,6 @@ hdl_library_clause_name = compaan_unb1_dp_offload_lib
hdl_lib_uses_synth = common unb1_board dp eth tech_tse diag ipcore
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
synth_files =
$HDL_BUILD_DIR/quartus/compaan_unb1_dp_offload/sopc_compaan_unb1_dp_offload.vhd
src/vhdl/pkg_signals.vhd
diff --git a/applications/compaan/libraries/hdllib.cfg b/applications/compaan/libraries/hdllib.cfg
index ef5e8bcac2797674e012c69ac1b0fd0af5b66abb..88538c1211caa775e184c104fd3d01828caf204c 100644
--- a/applications/compaan/libraries/hdllib.cfg
+++ b/applications/compaan/libraries/hdllib.cfg
@@ -4,10 +4,6 @@ hdl_lib_uses_synth = common technology ip_arria10_fifo ip_stratixiv_fifo tech_fi
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/compaandesign_com/common/common/1/hw_node_pkg.vhd
src/vhdl/compaandesign_com/common/altera/1/fsl_v20.vhd
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/altera/hdllib.cfg b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/altera/hdllib.cfg
index 6b3a4e9e8b462bb4c9477e969c8b6f0c1e8c9c7b..59e31486a09b20141c17d8efd131375996cc3369 100644
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/altera/hdllib.cfg
+++ b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/altera/hdllib.cfg
@@ -3,10 +3,6 @@ hdl_library_clause_name = compaandesign_com_common_altera_1_lib
hdl_lib_uses_synth = common dp
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/fsl_v20.vhd
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/common/hdllib.cfg b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/common/hdllib.cfg
index 226a664c4dd01a59a86e15fdca27e4ec54cc0180..9a26746e59ebc710762f1f6374bd0b69f1dfaaed 100644
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/common/hdllib.cfg
+++ b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/common/hdllib.cfg
@@ -3,10 +3,6 @@ hdl_library_clause_name = compaandesign_com_common_common_1_lib
hdl_lib_uses_synth =
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/hw_node_pkg.vhd
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/const_connector/hdllib.cfg b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/const_connector/hdllib.cfg
index 9aa4271c1ee4fe6963dee84ba4b95fd5b964e2b9..0e619a305d96c350893596fb4c43a7be05dc0dfa 100644
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/const_connector/hdllib.cfg
+++ b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/const_connector/hdllib.cfg
@@ -3,10 +3,6 @@ hdl_library_clause_name = compaandesign_com_common_const_connector_1_lib
hdl_lib_uses_synth =
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/const_connector.vhd
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/extern_connector/hdllib.cfg b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/extern_connector/hdllib.cfg
index 57d325d3b00421503e76a8aadfbb12dd174f3ceb..a0dfc627c1e5e6ffcfaa949c93632b1dca4cb3b2 100644
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/extern_connector/hdllib.cfg
+++ b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/extern_connector/hdllib.cfg
@@ -3,10 +3,6 @@ hdl_library_clause_name = compaandesign_com_common_extern_connector_1_lib
hdl_lib_uses_synth =
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/extern_connector.vhd
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/fifo/hdllib.cfg b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/fifo/hdllib.cfg
index bb8bef21e2cf2466b104f7ac880b29eae997217e..cea759101756a09041a0b1a27edd8e859795f8b6 100644
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/fifo/hdllib.cfg
+++ b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/fifo/hdllib.cfg
@@ -3,10 +3,6 @@ hdl_library_clause_name = compaandesign_com_common_fifo_1_lib
hdl_lib_uses_synth = compaandesign_com_common_altera_1
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/async_fifo_bram.vhd
src/vhdl/async_fifo.vhd
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/hwnode/hdllib.cfg b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/hwnode/hdllib.cfg
index c8d17afa1351b2352f52ca67848dd45afbb76f6f..9576a2dde2f5cf5bc7066248fe66e6c8f1b7cb03 100644
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/hwnode/hdllib.cfg
+++ b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/hwnode/hdllib.cfg
@@ -3,10 +3,6 @@ hdl_library_clause_name = compaandesign_com_common_hwnode_1_lib
hdl_lib_uses_synth = compaandesign_com_common_common_1 compaandesign_com_common_altera_1
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/controller.vhd
src/vhdl/counter.vhd
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/wire_connector/hdllib.cfg b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/wire_connector/hdllib.cfg
index b8d101bd9e597ecc0b76a20189a403122a9ddaa4..45248208078d355e374802f192b0616dd474027a 100644
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/wire_connector/hdllib.cfg
+++ b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/common/wire_connector/hdllib.cfg
@@ -3,10 +3,6 @@ hdl_library_clause_name = compaandesign_com_common_wire_connector_1_lib
hdl_lib_uses_synth =
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/wire_connector.vhd
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/control_if/hdllib.cfg b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/control_if/hdllib.cfg
index eec91446bdd0ba9deeebfb0061c6ea8334746e12..5c21947d7d89f4d79f15f93e77129b9ef50547dd 100644
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/control_if/hdllib.cfg
+++ b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/control_if/hdllib.cfg
@@ -3,10 +3,6 @@ hdl_library_clause_name = compaandesign_com_ipcore2RTL_control_if_1_lib
hdl_lib_uses_synth =
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/control_if.vhd
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_1/hdllib.cfg b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_1/hdllib.cfg
index 0dcd511e3dcd8558b263ba6985cbeefdd303dd76..e1efc20a5cba822b31fed65a22bf8b4f062ab575 100644
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_1/hdllib.cfg
+++ b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_1/hdllib.cfg
@@ -3,10 +3,6 @@ hdl_library_clause_name = compaandesign_com_ipcore2RTL_hwn_nd_1_1_lib
hdl_lib_uses_synth = compaandesign_com_common_hwnode_1 compaandesign_com_common_common_1
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/ipcore2RTL_hwn_nd_1_execution_unit.vhd
src/vhdl/ipcore2RTL_hwn_nd_1_eval_logic_rd.vhd
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_2/hdllib.cfg b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_2/hdllib.cfg
index 2186cf67ccbcbb6da539e90d7d917e5cc6dffb2d..68f60d2eaff3b12d42520c3fabce0cd7ff853582 100644
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_2/hdllib.cfg
+++ b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_2/hdllib.cfg
@@ -3,10 +3,6 @@ hdl_library_clause_name = compaandesign_com_ipcore2RTL_hwn_nd_2_1_lib
hdl_lib_uses_synth = compaandesign_com_common_hwnode_1 compaandesign_com_common_common_1
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/ipcore2RTL_hwn_nd_2_execution_unit.vhd
src/vhdl/ipcore2RTL_hwn_nd_2_eval_logic_rd.vhd
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_3/hdllib.cfg b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_3/hdllib.cfg
index 877deddba3435d675bb3c1f9502705409e3b590c..3378a88e561221d979a46bf2bbf7a43b9a27f507 100644
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_3/hdllib.cfg
+++ b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/hwn_nd_3/hdllib.cfg
@@ -3,10 +3,6 @@ hdl_library_clause_name = compaandesign_com_ipcore2RTL_hwn_nd_3_1_lib
hdl_lib_uses_synth = compaandesign_com_common_hwnode_1 compaandesign_com_common_common_1
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/ipcore2RTL_hwn_nd_3_execution_unit.vhd
src/vhdl/ipcore2RTL_hwn_nd_3_eval_logic_rd.vhd
diff --git a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/register_rf/hdllib.cfg b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/register_rf/hdllib.cfg
index b3a6db2f682300cd4dbf22fdeddf3e9aa8f52183..133b6ea234f126418c7467490da281470ce4cc53 100644
--- a/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/register_rf/hdllib.cfg
+++ b/applications/compaan/libraries/ipcore_trace/astron/compaandesign_com/ipcore2RTL/register_rf/hdllib.cfg
@@ -3,10 +3,6 @@ hdl_library_clause_name = compaandesign_com_ipcore2RTL_register_rf_1_lib
hdl_lib_uses_synth =
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/register_rf.vhd
diff --git a/applications/compaan/libraries/ipcore_trace/astron/hdllib.cfg b/applications/compaan/libraries/ipcore_trace/astron/hdllib.cfg
index 6d2c4e21247f3b324673d71391f160de50533247..2479f4683414a5148729888b86113420baa6357d 100644
--- a/applications/compaan/libraries/ipcore_trace/astron/hdllib.cfg
+++ b/applications/compaan/libraries/ipcore_trace/astron/hdllib.cfg
@@ -4,10 +4,6 @@ hdl_library_clause_name = ipcore_lib
hdl_lib_uses_synth = compaandesign_com_ipcore2RTL_hwn_nd_1_1 compaandesign_com_ipcore2RTL_hwn_nd_2_1 compaandesign_com_ipcore2RTL_register_rf_1 compaandesign_com_ipcore2RTL_hwn_nd_3_1 compaandesign_com_ipcore2RTL_control_if_1 compaandesign_com_common_altera_1
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
-# Specify here all the files you want to be included in the library.
synth_files =
src/vhdl/ipcore.vhd
src/vhdl/ipcore2RTL_control_if_ip_wrapper.vhd
diff --git a/applications/unb1_reorder/hdllib.cfg b/applications/unb1_reorder/hdllib.cfg
index 9116406787c75134683e616a448cb6187c820591..d52e31fb23f6ee72c797f8359c26e9c857629de4 100644
--- a/applications/unb1_reorder/hdllib.cfg
+++ b/applications/unb1_reorder/hdllib.cfg
@@ -6,9 +6,6 @@ hdl_lib_technology = ip_stratixiv
hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
synth_files =
$HDL_BUILD_DIR/quartus/unb1_reorder/sopc_unb1_reorder.vhd
src/vhdl/node_unb1_reorder.vhd
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
index 0180ba419e375ee3e8fa1ea0e34a422ce6f4ee53..44394899293ce9c3a273685b4f13fcf0dd0e280d 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
@@ -6,9 +6,6 @@ hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
synth_files =
$HDL_BUILD_DIR/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.vhd
src/vhdl/mmm_unb1_ddr3_transpose.vhd
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg b/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg
index 91e59a0611934abd25056d6fdf96bbdf8be41ce6..49ec32ae24cbd9909f53d9517cfa55692fdfc862 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg
@@ -3,9 +3,6 @@ hdl_library_clause_name = unb1_fn_terminal_db_lib
hdl_lib_uses_synth = common technology mm i2c unb1_board diag
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
synth_top_level_entity =
synth_files =
diff --git a/boards/uniboard1/designs/unb1_minimal/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/hdllib.cfg
index 6f58f3789e41c410a8739637a66f02af2b57bd54..38ec2880a86345e4a8baacd027804defda7c1098 100644
--- a/boards/uniboard1/designs/unb1_minimal/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/hdllib.cfg
@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
synth_files =
$HDL_BUILD_DIR/quartus/unb1_minimal_sopc/sopc_unb1_minimal.vhd
src/vhdl/qsys_unb1_minimal_pkg.vhd
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg
index d21104440186f45833f8c4ed67171bc18dc07a2a..04ce47b999e70e349655e145f24be58cf8cae488 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg
@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
synth_files =
unb1_minimal_qsys.vhd
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/hdllib.cfg
index 9dcd2ff6edad1a78848a9ff246ac9b78f036e968..7506bc963e515b37bf3c16d5865cbcab7b3d616b 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/hdllib.cfg
@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
synth_files =
unb1_minimal_sopc.vhd
diff --git a/boards/uniboard1/designs/unb1_test/hdllib.cfg b/boards/uniboard1/designs/unb1_test/hdllib.cfg
index 6b605bcfe4e6cba5ecb591e392bf25696d12865d..61cf80f99b80fcd44ea5537a092ea139efae33f8 100644
--- a/boards/uniboard1/designs/unb1_test/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/hdllib.cfg
@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
synth_files =
src/vhdl/qsys_unb1_test_pkg.vhd
src/vhdl/mmm_unb1_test.vhd
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg
index 45bdaf5311cdd9f1170d231dd843d5a50f49ad81..800e58990b94be1aaa866df19a9d4485fd2a4ec8 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg
@@ -6,9 +6,6 @@ hdl_lib_excludes = ip_stratixiv_ddr3_uphy_4g_800_slave
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
synth_files =
unb1_test_10GbE.vhd
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_lpbk/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_lpbk/hdllib.cfg
index 9ed48f71cc641564f254c1aeaa6b9dd610978db2..ed3020b2e6096f980bf582326ebef4dc7cb06504 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_lpbk/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_lpbk/hdllib.cfg
@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
synth_files =
unb1_test_lpbk.vhd
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_qsys/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_qsys/hdllib.cfg
index 52b1b693fcc834ab9fc67718b3c7b7cbc64dfce4..51c734ad037e693445e197bb84626a4b1605a527 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_qsys/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_qsys/hdllib.cfg
@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
synth_files =
unb1_test_qsys.vhd
diff --git a/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg b/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg
index b7136c61a6c4bc2e177e4d7608dd6365e39a0736..96f39d0fdf439c7359650dbd63d2201dad3914ad 100644
--- a/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg
@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
synth_files =
$HDL_BUILD_DIR/quartus/unb1_tr_10GbE/sopc_tr_10GbE.vhd
src/vhdl/node_unb1_tr_10GbE.vhd
diff --git a/boards/uniboard1/libraries/unb1_board/hdllib.cfg b/boards/uniboard1/libraries/unb1_board/hdllib.cfg
index c986eb0695de1eb459e509107ad1e37438069e70..a047b9247c98ce02d042a61205be3e938d037e0e 100644
--- a/boards/uniboard1/libraries/unb1_board/hdllib.cfg
+++ b/boards/uniboard1/libraries/unb1_board/hdllib.cfg
@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
synth_files =
src/vhdl/unb1_board_pkg.vhd
src/vhdl/unb1_board_system_info.vhd
diff --git a/boards/uniboard2/designs/unb2_minimal/hdllib.cfg b/boards/uniboard2/designs/unb2_minimal/hdllib.cfg
index 7f093c26788c5d7078d9552932985973828cfcc5..cc6e60105c1e9af3cd3aa82f8d977a0e62358009 100644
--- a/boards/uniboard2/designs/unb2_minimal/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_minimal/hdllib.cfg
@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
synth_files =
src/vhdl/qsys_unb2_minimal_pkg.vhd
src/vhdl/mmm_unb2_minimal.vhd
diff --git a/boards/uniboard2/designs/unb2_test/hdllib.cfg b/boards/uniboard2/designs/unb2_test/hdllib.cfg
index 2da94e97f65e3e37d6eb6483287039c1cd0e98a7..2a802bf67fffcb0b98a542fb3c1d8213eb34e6c2 100644
--- a/boards/uniboard2/designs/unb2_test/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/hdllib.cfg
@@ -7,9 +7,6 @@ hdl_lib_technology = ip_arria10
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
synth_files =
src/vhdl/qsys_unb2_test_pkg.vhd
src/vhdl/mmm_unb2_test.vhd
diff --git a/boards/uniboard2/libraries/unb2_board/hdllib.cfg b/boards/uniboard2/libraries/unb2_board/hdllib.cfg
index 8d1245b17dca2e0d78483f6fc95682cfc5e48b56..2d910fbbc26b3473f749005109b012d3a714f0f1 100644
--- a/boards/uniboard2/libraries/unb2_board/hdllib.cfg
+++ b/boards/uniboard2/libraries/unb2_board/hdllib.cfg
@@ -5,9 +5,6 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10
-build_dir_sim = $HDL_BUILD_DIR
-build_dir_synth = $HDL_BUILD_DIR
-
synth_files =
src/vhdl/unb2_board_pkg.vhd
src/vhdl/unb2_board_system_info.vhd
diff --git a/tools/hdltool.cfg b/tools/hdltool.cfg
index 104a3fe1f11dab7116ead9c70097f108d04cc9f5..c0314e56e36f0892b1141111190d3365573f1f9a 100644
--- a/tools/hdltool.cfg
+++ b/tools/hdltool.cfg
@@ -1,3 +1,6 @@
+build_dir_sim = $HDL_BUILD_DIR
tool_name_sim = modelsim
-tool_name_synth = quartus
model_tech_dir = /home/software/Mentor/6.6c/modeltech
+
+build_dir_synth = $HDL_BUILD_DIR
+tool_name_synth = quartus
diff --git a/tools/hdltool_readme.txt b/tools/hdltool_readme.txt
index 607b7e317b0b5237f5d99ed92afa530af700afb1..1f0e711a5dc9d027d9489920225f8551618fc040 100644
--- a/tools/hdltool_readme.txt
+++ b/tools/hdltool_readme.txt
@@ -319,6 +319,14 @@ See also the docstring help text in the Python code:
c) hdltool.cfg key descriptions
+- build_dir_sim =
+ Global root path (e.g. $HDL_BUILD_DIR) to the build directory for simulation. The path gets extended with the
+ tool_name_sim from hdltool.cfg.
+
+- build_dir_synth =
+ Global root path (e.g. $HDL_BUILD_DIR) to the build directory for simulation. The path gets extended with the
+ tool_name_synth from hdltool.cfg.
+
- tool_name_sim =
Used as directory name in the build directory, e.g. modelsim.
@@ -364,14 +372,6 @@ d) hdllib.cfg key descriptions
The IP technology that this library is using or targets, e.g. ip_stratixiv for UniBoard1, ip_arria10 for UniBoard2. For generic HDL libraries use ''.
For simulating systems with multiple FPGA technologies it is also possible to list multiple IP technology names.
-- build_dir_sim =
- Global root path (e.g. $HDL_BUILD_DIR) or local library path (e.g. '') to the build directory for simulation. The path gets extended with the
- tool_name_sim from hdltool.cfg.
-
-- build_dir_synth =
- Global root path (e.g. $HDL_BUILD_DIR) or local library path (e.g. '') to the build directory for simulation. The path gets extended with the
- tool_name_synth from hdltool.cfg.
-
- modelsim_compile_ip_files =
This key lists one or more TCL scripts that are executed by the Modelsim mpf before it compiles the rest of the source code. Eg:
- compile_ip.tcl : a TCL script that contains external IP sources that are fixed and need to be compiled before the synth_files. For
@@ -461,23 +461,15 @@ find the new avs2_eth_coe in $RADIOHDL.
5) Build directory location
-The Modelsim and Quartus build location can be local to the HDL library directory:
-
- <hdl_lib_name>/hdllib.cfg
- quartus/
- modelsim/
- src/vhdl/
- tb/vhdl/
-
-or central outside the $RADIOHDL sources directory tree:
+The Modelsim and Quartus build location central outside the $RADIOHDL sources directory tree:
$HDL_BUILD_DIR/quartus/<hdl_lib_name>
/modelsim/<hdl_lib_name>
-The choice is made via the build_dir_sim and build_dir_synth keys. If the key is left empty than the build directory will be
-local else the key should specify the root path to the central directory e.g.via $HDL_BUILD_DIR. The advantage of the central
-directory build tree is that it can easily be removed (using rm -rf) and recreated (using modelsim_config.py and quartus_config.py).
-For synthesis recreation of targets like sof files can take much time though.
+The location is made via the build_dir_sim and build_dir_synth keys that specify the root path to the central directory e.g.
+via $HDL_BUILD_DIR. The advantage of the central directory build tree is that it can easily be removed (using rm -rf) and
+recreated (using modelsim_config.py and quartus_config.py). For synthesis recreation of targets like sof files can take much
+time though.
@@ -485,10 +477,9 @@ For synthesis recreation of targets like sof files can take much time though.
a) Creating the Modelsim project files
-The binaries for Modelsim get build in a separate directory tree if the build_dir_sim key in the hdllib.cfg contains
-an absolute path. Currently the path is set to $HDL_BUILD_DIR = $RADIOHDL/build. By using a local path for the
-build_dir_sim key it is possible to build the library locally in the source directory tree, however using a completely
-separate absolute build tree is more clear. To create the Modelsim project files for all HDL libraries in the $RADIOHDL tree do:
+The binaries for Modelsim get build in a separate directory tree with absolute path set by the build_dir_sim key in the hdltool.cfg.
+Currently the path is set to $HDL_BUILD_DIR = $RADIOHDL/build. Using a completely separate absolute build tree is more clear than
+building the library in a local build directory. To create the Modelsim project files for all HDL libraries in the $RADIOHDL tree do:
$RADIOHDL> rm -rf build
$RADIOHDL> python modelsim_config.py
@@ -726,9 +717,9 @@ h) hdltool.cfg per toolset (see also i, j, k)
model_tech_dir = /home/software/Mentor/10.4/modeltech
Currently the 6.6c modelsim.ini is used even if Modelsim 10.4 is ran.
- . The build_dir_sim and build_dir_synth are defined in the hdllib.cfg and both set to $HDL_BUILD_DIR. It seems
- better to define these keys in the hdltool.cfg, because currently all they are thesame in all hdllib.cfg and
- with the possibility to define different hdltool.cfg there is already enough freedom.
+ . (FIXED erko) The build_dir_sim and build_dir_synth are now defined in the hdltool.cfg instead of in each
+ hdllib.cfg. It seems better to define these keys in the hdltool.cfg, because currently all they are the same
+ in all hdllib.cfg and with the possibility to define different hdltool.cfg there is already enough freedom.
Conclusion:
- Is the hdltool.cfg necessary/useful at all? Yes. Keep hdltool.cfg, but define dedicated hdltool_<toolset>.cfg
@@ -741,11 +732,12 @@ i) multiple libRootDirs for finding hdllib.cfg files
could be a very large tree to search through. Furthermore by being able to specify the rootDirs more precisely
avoids finding unintended hdllib.cfg files.
-j) Central build tree or local build directory
+j) (FIXED - erko) Central build tree or local build directory
The get_lib_build_dirs() in hdl_config.cfg provides the option to build the sources locally in the library
directory or in a central build tree. The central build tree is preferred, because the local build in the library
is scattered and fills the SVN tree with build files. The local build option is not used. Therefore it may be
better and more clear to completely remove the support to do a local build from get_lib_build_dirs().
+ --> fixed: the build_dir key now must specify a build directory.
k) Support multiple --technology
It should be possible to define multiple technologies at the --technology option. As long as Modelsim supports
diff --git a/tools/oneclick/base/hdl_config.py b/tools/oneclick/base/hdl_config.py
index 9e8351c6da25dd43bbdaf0b18364c3845e059fa2..1904c3da1ec637650c6b99f65415e0f720a09dc3 100644
--- a/tools/oneclick/base/hdl_config.py
+++ b/tools/oneclick/base/hdl_config.py
@@ -193,17 +193,18 @@ class HdlConfig:
if lib_dicts==None: lib_dicts=self.libs.dicts
build_dir_key = 'build_dir_' + build_type
tool_name_key = 'tool_name_' + build_type
+ if self.tool.get_key_values(build_dir_key)==None:
+ sys.exit('Error : Unknown build type for build_dir_key')
+ build_maindir = os.path.expandvars(self.tool.get_key_values(build_dir_key))
+ if not os.path.isabs(build_maindir):
+ sys.exit('Error : The build_dir_key value must be an absolute path')
if self.tool.get_key_values(tool_name_key)==None:
- sys.exit('Error : Unknown build type')
+ sys.exit('Error : Unknown build type for tool_name_key')
build_subdir = self.tool.get_key_values(tool_name_key)
build_dirs = []
for lib_dict in cm.listify(lib_dicts):
lib_name = lib_dict['hdl_lib_name']
- build_dir = os.path.expandvars(self.libs.get_key_values(build_dir_key, lib_dict))
- if build_dir=='':
- sys.exit('Error : The build_dir key in %s must specify a build directory (default to local build directory within the HDL library directory is not supported)' % lib_name)
- else:
- build_dirs.append(os.path.join(build_dir, build_subdir, lib_name)) # central build cdirectory
+ build_dirs.append(os.path.join(build_maindir, build_subdir, lib_name)) # central build main directory with subdirectory per library
return cm.unlistify(build_dirs)
def create_lib_order_files(self, build_type, lib_names=None):
@@ -386,7 +387,7 @@ if __name__ == '__main__':
hdl.libs.rename_key_in_dict_file(p, old_key, new_key)
if mode==5:
- remove_key = 'synth_revision'
+ remove_key = 'build_dir_synth'
# Read the dictionary info from all HDL tool and library configuration files in the current directory and the sub directories
libRootDir = 'RADIOHDL'
hdl = HdlConfig(libRootDir=os.environ[libRootDir], toolRootDir=os.path.expandvars('$RADIOHDL/tools'), libFileName='hdllib.cfg', toolFileName='hdltool.cfg', technologyNames=[])