added the ETH_CLK of 125MHz option

boards/uniboard2/libraries/unb2_board/hdllib.cfg

@@ -14,6 +14,7 @@ synth_files =
     src/vhdl/unb2_board_clk_rst.vhd
     src/vhdl/unb2_board_clk200_pll.vhd
     src/vhdl/unb2_board_clk25_pll.vhd
+    src/vhdl/unb2_board_clk125_pll.vhd
     src/vhdl/unb2_board_pulser.vhd
     src/vhdl/unb2_board_wdi_extend.vhd
     src/vhdl/unb2_board_node_ctrl.vhd

boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc

@@ -23,9 +23,11 @@
 set_time_format -unit ns -decimal_places 3
 
 create_clock -name {CLK} -period 5.000 -waveform { 0.000 2.500 } [get_ports {CLK}]
-create_clock -name {ETH_CLK} -period 40.000 -waveform { 0.000 20.000 } [get_ports {ETH_clk}]
-#create_clock -name {SB_CLK} -period 6.400 -waveform { 0.000 3.200 } [get_ports {SB_CLK}]
-#create_clock -name {SA_CLK} -period 6.400 -waveform { 0.000 3.200 } [get_ports {SA_CLK}]
+#create_clock -name {ETH_CLK} -period 40.000 -waveform { 0.000 20.000 } [get_ports {ETH_CLK}]
+create_clock -name {ETH_CLK} -period 8.000 -waveform { 0.000 4.000 } [get_ports {ETH_CLK}]
+
+create_clock -name {SB_CLK} -period 6.400 -waveform { 0.000 3.200 } [get_ports {SB_CLK}]
+create_clock -name {SA_CLK} -period 6.400 -waveform { 0.000 3.200 } [get_ports {SA_CLK}]
 
 derive_pll_clocks
 
@@ -33,12 +35,16 @@ derive_clock_uncertainty
 
 # Effectively set false path from this clock to all other clocks
 set_clock_groups -asynchronous -group [get_clocks altera_reserved_tck]
-#set_clock_groups -asynchronous -group [get_clocks SB_CLK]
-#set_clock_groups -asynchronous -group [get_clocks SA_CLK]
+set_clock_groups -asynchronous -group [get_clocks SB_CLK]
+set_clock_groups -asynchronous -group [get_clocks SA_CLK]
 set_clock_groups -asynchronous -group [get_clocks ETH_CLK]
 set_clock_groups -asynchronous -group [get_clocks CLK]
 set_clock_groups -asynchronous -group [get_clocks pll_clk20]
 set_clock_groups -asynchronous -group [get_clocks pll_clk50]
+set_clock_groups -asynchronous -group [get_clocks pll_clk100]
 set_clock_groups -asynchronous -group [get_clocks pll_clk125]
-set_clock_groups -asynchronous -group [get_clocks u_ctrl|\gen_pll:u_unb2_board_clk200_pll|u_st_pll|\gen_ip_arria10:u0|iopll_0|outclk0]
+
+set_clock_groups -asynchronous -group [get_clocks pll_clk200]
+set_clock_groups -asynchronous -group [get_clocks pll_clk200p]
+set_clock_groups -asynchronous -group [get_clocks pll_clk400]