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RTSD
HDL
Commits
f581db6b
Commit
f581db6b
authored
1 year ago
by
Eric Kooistra
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Support g_use_complex
parent
3e53d732
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1 merge request
!339
Resolve L2SDP-959
Pipeline
#55520
passed
1 year ago
Stage: linting
Changes
1
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1
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libraries/base/reorder/src/vhdl/reorder_row_select.vhd
+19
-6
19 additions, 6 deletions
libraries/base/reorder/src/vhdl/reorder_row_select.vhd
with
19 additions
and
6 deletions
libraries/base/reorder/src/vhdl/reorder_row_select.vhd
+
19
−
6
View file @
f581db6b
...
@@ -45,6 +45,7 @@ entity reorder_row_select is
...
@@ -45,6 +45,7 @@ entity reorder_row_select is
g_dsp_data_w
:
natural
:
=
16
;
-- complex data width, = c_data_w / 2
g_dsp_data_w
:
natural
:
=
16
;
-- complex data width, = c_data_w / 2
g_nof_inputs
:
natural
:
=
8
;
g_nof_inputs
:
natural
:
=
8
;
g_nof_outputs
:
natural
:
=
16
;
g_nof_outputs
:
natural
:
=
16
;
g_use_complex
:
boolean
:
=
true
;
g_pipeline_in
:
natural
:
=
1
;
-- pipeline in_data
g_pipeline_in
:
natural
:
=
1
;
-- pipeline in_data
g_pipeline_in_m
:
natural
:
=
1
;
-- pipeline in_data for M-fold fan out
g_pipeline_in_m
:
natural
:
=
1
;
-- pipeline in_data for M-fold fan out
g_pipeline_out
:
natural
:
=
1
-- pipeline out_data
g_pipeline_out
:
natural
:
=
1
-- pipeline out_data
...
@@ -87,9 +88,15 @@ begin
...
@@ -87,9 +88,15 @@ begin
-- selection buffer.
-- selection buffer.
---------------------------------------------------------------
---------------------------------------------------------------
gen_input
:
for
I
in
g_nof_inputs
-
1
downto
0
generate
gen_input
:
for
I
in
g_nof_inputs
-
1
downto
0
generate
reorder_in_dat
((
I
+
1
)
*
c_data_w
-
1
downto
I
*
c_data_w
)
<=
use_complex
:
if
g_use_complex
generate
input_sosi_arr
(
I
)
.
im
(
g_dsp_data_w
-
1
downto
0
)
&
reorder_in_dat
((
I
+
1
)
*
c_data_w
-
1
downto
I
*
c_data_w
)
<=
input_sosi_arr
(
I
)
.
re
(
g_dsp_data_w
-
1
downto
0
);
input_sosi_arr
(
I
)
.
im
(
g_dsp_data_w
-
1
downto
0
)
&
input_sosi_arr
(
I
)
.
re
(
g_dsp_data_w
-
1
downto
0
);
end
generate
;
use_data
:
if
not
g_use_complex
generate
reorder_in_dat
((
I
+
1
)
*
c_data_w
-
1
downto
I
*
c_data_w
)
<=
input_sosi_arr
(
I
)
.
data
(
c_data_w
-
1
downto
0
);
end
generate
;
end
generate
;
end
generate
;
---------------------------------------------------------------
---------------------------------------------------------------
...
@@ -125,19 +132,25 @@ begin
...
@@ -125,19 +132,25 @@ begin
---------------------------------------------------------------
---------------------------------------------------------------
comb
:
process
(
r
,
input_sosi_arr
,
reorder_out_dat
)
comb
:
process
(
r
,
input_sosi_arr
,
reorder_out_dat
)
variable
v
:
reg_type
;
variable
v
:
reg_type
;
-- Use intermediate variables to avoid too long code lines
variable
v_re
:
std_logic_vector
(
g_dsp_data_w
-
1
downto
0
);
variable
v_im
:
std_logic_vector
(
g_dsp_data_w
-
1
downto
0
);
begin
begin
v
:
=
r
;
v
:
=
r
;
v
.
pipe_sosi_2arr
(
0
)
:
=
input_sosi_arr
;
v
.
pipe_sosi_2arr
(
0
)
:
=
input_sosi_arr
;
v
.
pipe_sosi_2arr
(
c_tot_pipeline
-1
downto
1
)
:
=
r
.
pipe_sosi_2arr
(
c_tot_pipeline
-2
downto
0
);
v
.
pipe_sosi_2arr
(
c_tot_pipeline
-1
downto
1
)
:
=
r
.
pipe_sosi_2arr
(
c_tot_pipeline
-2
downto
0
);
-- Merge data output to the outgoing SOSI record.
-- Merge data output to the outgoing SOSI record.
-- Assigning re,im is don't care when g_use_complex is false.
for
I
in
g_nof_outputs
-
1
downto
0
loop
for
I
in
g_nof_outputs
-
1
downto
0
loop
v_im
:
=
reorder_out_dat
((
I
+
1
)
*
c_data_w
-
1
downto
I
*
c_data_w
+
g_dsp_data_w
);
v_re
:
=
reorder_out_dat
((
I
+
1
)
*
c_data_w
-
g_dsp_data_w
-
1
downto
I
*
c_data_w
);
v
.
output_sosi_arr
(
I
)
:
=
r
.
pipe_sosi_2arr
(
c_tot_pipeline
-1
)(
0
);
v
.
output_sosi_arr
(
I
)
:
=
r
.
pipe_sosi_2arr
(
c_tot_pipeline
-1
)(
0
);
v
.
output_sosi_arr
(
I
)
.
im
:
=
RESIZE_DP_DSP_DATA
(
reorder_out_dat
((
I
+
1
)
*
c_data_w
-
1
downto
I
*
c_data_w
+
g_dsp_data_w
)
);
v
.
output_sosi_arr
(
I
)
.
im
:
=
RESIZE_DP_DSP_DATA
(
v_im
);
v
.
output_sosi_arr
(
I
)
.
re
:
=
RESIZE_DP_DSP_DATA
(
re
order_out_dat
((
I
+
1
)
*
c_data_w
-
g_dsp_data_w
-
1
downto
I
*
c_data_w
)
);
v
.
output_sosi_arr
(
I
)
.
re
:
=
RESIZE_DP_DSP_DATA
(
v_
re
);
end
loop
;
end
loop
;
rin
<=
v
;
rin
<=
v
;
end
process
comb
;
end
process
comb
;
regs
:
process
(
dp_clk
)
regs
:
process
(
dp_clk
)
...
...
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