From f581db6b4b1926543a62dde9a09e9755a6a3c3a6 Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Thu, 10 Aug 2023 09:05:57 +0200
Subject: [PATCH] Support g_use_complex
---
.../reorder/src/vhdl/reorder_row_select.vhd | 25 ++++++++++++++-----
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git a/libraries/base/reorder/src/vhdl/reorder_row_select.vhd b/libraries/base/reorder/src/vhdl/reorder_row_select.vhd
index b737cbe147..0dfa93f62c 100644
--- a/libraries/base/reorder/src/vhdl/reorder_row_select.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_row_select.vhd
@@ -45,6 +45,7 @@ entity reorder_row_select is
g_dsp_data_w : natural := 16; -- complex data width, = c_data_w / 2
g_nof_inputs : natural := 8;
g_nof_outputs : natural := 16;
+ g_use_complex : boolean := true;
g_pipeline_in : natural := 1; -- pipeline in_data
g_pipeline_in_m : natural := 1; -- pipeline in_data for M-fold fan out
g_pipeline_out : natural := 1 -- pipeline out_data
@@ -87,9 +88,15 @@ begin
-- selection buffer.
---------------------------------------------------------------
gen_input : for I in g_nof_inputs - 1 downto 0 generate
- reorder_in_dat((I + 1) * c_data_w - 1 downto I * c_data_w) <=
- input_sosi_arr(I).im(g_dsp_data_w - 1 downto 0) &
- input_sosi_arr(I).re(g_dsp_data_w - 1 downto 0);
+ use_complex : if g_use_complex generate
+ reorder_in_dat((I + 1) * c_data_w - 1 downto I * c_data_w) <=
+ input_sosi_arr(I).im(g_dsp_data_w - 1 downto 0) &
+ input_sosi_arr(I).re(g_dsp_data_w - 1 downto 0);
+ end generate;
+ use_data : if not g_use_complex generate
+ reorder_in_dat((I + 1) * c_data_w - 1 downto I * c_data_w) <=
+ input_sosi_arr(I).data(c_data_w - 1 downto 0);
+ end generate;
end generate;
---------------------------------------------------------------
@@ -125,19 +132,25 @@ begin
---------------------------------------------------------------
comb : process(r, input_sosi_arr, reorder_out_dat)
variable v : reg_type;
+ -- Use intermediate variables to avoid too long code lines
+ variable v_re : std_logic_vector(g_dsp_data_w - 1 downto 0);
+ variable v_im : std_logic_vector(g_dsp_data_w - 1 downto 0);
begin
v := r;
v.pipe_sosi_2arr(0) := input_sosi_arr;
v.pipe_sosi_2arr(c_tot_pipeline-1 downto 1) := r.pipe_sosi_2arr(c_tot_pipeline-2 downto 0);
-- Merge data output to the outgoing SOSI record.
+ -- Assigning re,im is don't care when g_use_complex is false.
for I in g_nof_outputs - 1 downto 0 loop
+ v_im := reorder_out_dat((I + 1) * c_data_w - 1 downto I * c_data_w + g_dsp_data_w);
+ v_re := reorder_out_dat((I + 1) * c_data_w - g_dsp_data_w - 1 downto I * c_data_w);
v.output_sosi_arr(I) := r.pipe_sosi_2arr(c_tot_pipeline-1)(0);
- v.output_sosi_arr(I).im := RESIZE_DP_DSP_DATA(reorder_out_dat((I + 1) * c_data_w - 1 downto I * c_data_w + g_dsp_data_w));
- v.output_sosi_arr(I).re := RESIZE_DP_DSP_DATA(reorder_out_dat((I + 1) * c_data_w - g_dsp_data_w - 1 downto I * c_data_w));
+ v.output_sosi_arr(I).im := RESIZE_DP_DSP_DATA(v_im);
+ v.output_sosi_arr(I).re := RESIZE_DP_DSP_DATA(v_re);
end loop;
- rin <= v;
+ rin <= v;
end process comb;
regs : process(dp_clk)
--
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