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Commit f248d57e authored by Daniel van der Schuur's avatar Daniel van der Schuur
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-Stripped down the VHDL files; 

-Fixed paths in hdllib;
-Adjusted MM width of BG in SOPC.
parent 207e5ba7
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with 89 additions and 826 deletions
applications/apertif/designs/apertif_unb1_fn_bf_emu/hdllib.cfg
+ 2
− 2
View file @ f248d57e
...@@ -11,12 +11,12 @@ synth_top_level_entity = ...@@ -11,12 +11,12 @@ synth_top_level_entity =
synth_files = synth_files =
$HDL_BUILD_DIR/unb1/quartus/apertif_unb1_fn_bf_emu/sopc_apertif_unb1_fn_bf_emu.vhd $HDL_BUILD_DIR/unb1/quartus/apertif_unb1_fn_bf_emu/sopc_apertif_unb1_fn_bf_emu.vhd
../apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_bf_emu_udp_offload.vhd ../apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer_udp_offload.vhd
src/vhdl/mmm_apertif_unb1_fn_bf_emu.vhd src/vhdl/mmm_apertif_unb1_fn_bf_emu.vhd
src/vhdl/apertif_unb1_fn_bf_emu.vhd src/vhdl/apertif_unb1_fn_bf_emu.vhd
test_bench_files = test_bench_files =
tb_apertif_unb1_fn_bf_emu.vhd tb/vhdl/tb_apertif_unb1_fn_bf_emu.vhd
modelsim_copy_files = src/hex hex modelsim_copy_files = src/hex hex
......
applications/apertif/designs/apertif_unb1_fn_bf_emu/quartus/sopc_apertif_unb1_fn_bf_emu.sopc
+ 39
− 39
View file @ f248d57e
...@@ -92,6 +92,14 @@ ...@@ -92,6 +92,14 @@
type = "String"; type = "String";
} }
} }
element ram_diag_bg.mem
{
datum baseAddress
{
value = "32768";
type = "long";
}
}
element reg_mdio_2.mem element reg_mdio_2.mem
{ {
datum baseAddress datum baseAddress
...@@ -100,7 +108,7 @@ ...@@ -100,7 +108,7 @@
type = "long"; type = "long";
} }
} }
element rom_system_info.mem element reg_wdi.mem
{ {
datum _lockedAddress datum _lockedAddress
{ {
...@@ -109,19 +117,11 @@ ...@@ -109,19 +117,11 @@
} }
datum baseAddress datum baseAddress
{ {
value = "4096"; value = "12288";
type = "long";
}
}
element ram_diag_bg.mem
{
datum baseAddress
{
value = "32768";
type = "long"; type = "long";
} }
} }
element pio_system_info.mem element rom_system_info.mem
{ {
datum _lockedAddress datum _lockedAddress
{ {
...@@ -130,68 +130,68 @@ ...@@ -130,68 +130,68 @@
} }
datum baseAddress datum baseAddress
{ {
value = "0"; value = "4096";
type = "long"; type = "long";
} }
} }
element reg_wdi.mem element reg_mdio_0.mem
{
datum _lockedAddress
{ {
value = "1";
type = "boolean";
}
datum baseAddress datum baseAddress
{ {
value = "12288"; value = "288";
type = "long"; type = "long";
} }
} }
element reg_diag_bg.mem element reg_mdio_1.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "256"; value = "320";
type = "long"; type = "long";
} }
} }
element pio_pps.mem element pio_system_info.mem
{
datum _lockedAddress
{ {
value = "1";
type = "boolean";
}
datum baseAddress datum baseAddress
{ {
value = "440"; value = "0";
type = "long"; type = "long";
} }
} }
element reg_mdio_0.mem element pio_pps.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "288"; value = "440";
type = "long"; type = "long";
} }
} }
element reg_tr_xaui.mem element reg_unb_sens.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "16384"; value = "224";
type = "long"; type = "long";
} }
} }
element reg_mdio_1.mem element reg_diag_bg.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "320"; value = "256";
type = "long"; type = "long";
} }
} }
element reg_unb_sens.mem element reg_tr_xaui.mem
{ {
datum baseAddress datum baseAddress
{ {
value = "224"; value = "16384";
type = "long"; type = "long";
} }
} }
...@@ -388,19 +388,19 @@ ...@@ -388,19 +388,19 @@
type = "long"; type = "long";
} }
} }
element timer_0.s1 element pio_debug_wave.s1
{ {
datum baseAddress datum baseAddress
{ {
value = "192"; value = "400";
type = "long"; type = "long";
} }
} }
element pio_debug_wave.s1 element timer_0.s1
{ {
datum baseAddress datum baseAddress
{ {
value = "400"; value = "192";
type = "long"; type = "long";
} }
} }
...@@ -447,8 +447,8 @@ ...@@ -447,8 +447,8 @@
<parameter name="maxAdditionalLatency" value="0" /> <parameter name="maxAdditionalLatency" value="0" />
<parameter name="projectName">apertif_unb1_fn_bf_emu.qpf</parameter> <parameter name="projectName">apertif_unb1_fn_bf_emu.qpf</parameter>
<parameter name="sopcBorderPoints" value="true" /> <parameter name="sopcBorderPoints" value="true" />
<parameter name="systemHash" value="-38264576650" /> <parameter name="systemHash" value="-36816734619" />
<parameter name="timeStamp" value="1432881833399" /> <parameter name="timeStamp" value="1432887284815" />
<parameter name="useTestBenchNamingPattern" value="false" /> <parameter name="useTestBenchNamingPattern" value="false" />
<module kind="clock_source" version="11.1" enabled="1" name="clk_0"> <module kind="clock_source" version="11.1" enabled="1" name="clk_0">
<parameter name="clockFrequency" value="25000000" /> <parameter name="clockFrequency" value="25000000" />
...@@ -549,7 +549,7 @@ ...@@ -549,7 +549,7 @@
<parameter name="dcache_numTCDM" value="_0" /> <parameter name="dcache_numTCDM" value="_0" />
<parameter name="dcache_lineSize" value="_32" /> <parameter name="dcache_lineSize" value="_32" />
<parameter name="dcache_bursts" value="false" /> <parameter name="dcache_bursts" value="false" />
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='timer_0.s1' start='0xC0' end='0xE0' /><slave name='reg_unb_sens.mem' start='0xE0' end='0x100' /><slave name='reg_diag_bg.mem' start='0x100' end='0x120' /><slave name='reg_mdio_0.mem' start='0x120' end='0x140' /><slave name='reg_mdio_1.mem' start='0x140' end='0x160' /><slave name='reg_mdio_2.mem' start='0x160' end='0x180' /><slave name='altpll_0.pll_slave' start='0x180' end='0x190' /><slave name='pio_debug_wave.s1' start='0x190' end='0x1A0' /><slave name='pio_wdi.s1' start='0x1A0' end='0x1B0' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x1B0' end='0x1B8' /><slave name='pio_pps.mem' start='0x1B8' end='0x1C0' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='reg_tr_xaui.mem' start='0x4000' end='0x6000' /><slave name='avs_eth_0.mms_ram' start='0x6000' end='0x7000' /><slave name='ram_diag_bg.mem' start='0x8000' end='0x10000' /><slave name='reg_tr_10GbE.mem' start='0x10000' end='0x18000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter> <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='timer_0.s1' start='0xC0' end='0xE0' /><slave name='reg_unb_sens.mem' start='0xE0' end='0x100' /><slave name='reg_diag_bg.mem' start='0x100' end='0x120' /><slave name='reg_mdio_0.mem' start='0x120' end='0x140' /><slave name='reg_mdio_1.mem' start='0x140' end='0x160' /><slave name='reg_mdio_2.mem' start='0x160' end='0x180' /><slave name='altpll_0.pll_slave' start='0x180' end='0x190' /><slave name='pio_debug_wave.s1' start='0x190' end='0x1A0' /><slave name='pio_wdi.s1' start='0x1A0' end='0x1B0' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x1B0' end='0x1B8' /><slave name='pio_pps.mem' start='0x1B8' end='0x1C0' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='reg_tr_xaui.mem' start='0x4000' end='0x6000' /><slave name='avs_eth_0.mms_ram' start='0x6000' end='0x7000' /><slave name='ram_diag_bg.mem' start='0x8000' end='0x9000' /><slave name='reg_tr_10GbE.mem' start='0x10000' end='0x18000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
<parameter name="dataAddrWidth" value="18" /> <parameter name="dataAddrWidth" value="18" />
<parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" /> <parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
<parameter name="cpuReset" value="false" /> <parameter name="cpuReset" value="false" />
...@@ -833,7 +833,7 @@ q]]></parameter> ...@@ -833,7 +833,7 @@ q]]></parameter>
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" /> <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
</module> </module>
<module kind="avs_common_mm" version="1.0" enabled="1" name="ram_diag_bg"> <module kind="avs_common_mm" version="1.0" enabled="1" name="ram_diag_bg">
<parameter name="g_adr_w" value="13" /> <parameter name="g_adr_w" value="10" />
<parameter name="g_dat_w" value="32" /> <parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" /> <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
</module> </module>
......
applications/apertif/designs/apertif_unb1_fn_bf_emu/src/vhdl/apertif_unb1_fn_bf_emu.vhd
+ 29
− 465
View file @ f248d57e
...@@ -75,17 +75,6 @@ ENTITY apertif_unb1_fn_bf_emu IS ...@@ -75,17 +75,6 @@ ENTITY apertif_unb1_fn_bf_emu IS
-- Transceiver clocks -- Transceiver clocks
SA_CLK : IN STD_LOGIC := '0'; -- TR clock BN-BI (tr_back) / SI_FN (tr_front) SA_CLK : IN STD_LOGIC := '0'; -- TR clock BN-BI (tr_back) / SI_FN (tr_front)
SB_CLK : IN STD_LOGIC := '0'; -- TR clock FN-BN (tr_mesh)
-- Mesh Serial I/O
FN_BN_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
FN_BN_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
FN_BN_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
FN_BN_1_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
FN_BN_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
FN_BN_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
FN_BN_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
FN_BN_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
-- Front Serial I/O -- Front Serial I/O
SI_FN_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0); SI_FN_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
...@@ -101,25 +90,17 @@ ENTITY apertif_unb1_fn_bf_emu IS ...@@ -101,25 +90,17 @@ ENTITY apertif_unb1_fn_bf_emu IS
SI_FN_1_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0); SI_FN_1_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
SI_FN_2_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0); SI_FN_2_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
SI_FN_3_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0); SI_FN_3_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
SI_FN_RSTN : OUT STD_LOGIC := '1'; -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor. SI_FN_RSTN : OUT STD_LOGIC := '1' -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
-- So we need to assign a '1' to it. -- So we need to assign a '1' to it.
-- SO-DIMM Memory Bank I
MB_I_IN : IN t_tech_ddr3_phy_in;
MB_I_IO : INOUT t_tech_ddr3_phy_io;
MB_I_OU : OUT t_tech_ddr3_phy_ou
); );
END apertif_unb1_fn_bf_emu; END apertif_unb1_fn_bf_emu;
ARCHITECTURE str OF apertif_unb1_fn_bf_emu IS ARCHITECTURE str OF apertif_unb1_fn_bf_emu IS
CONSTANT c_use_transpose : BOOLEAN := g_design_name="apertif_unb1_fn_bf_emu_trans" OR g_design_name="apertif_unb1_fn_bf_emu_tp_bg"; -- Also use DDR3 CONSTANT c_use_phy : t_c_unb1_board_use_phy := (1, 1, 0, 0, 0, 0, 0, 1);
CONSTANT c_use_bg : BOOLEAN := g_design_name="apertif_unb1_fn_bf_emu_tp_bg"; -- Also use DDR3, but no mesh terminals CONSTANT c_fw_version : t_unb1_board_fw_version := (0, 0); -- firmware version x.y
CONSTANt c_use_bf : BOOLEAN := NOT(g_design_name="apertif_unb1_fn_bf_emu_tp_bg" AND g_sim); CONSTANT c_dp_clk_use_pll : BOOLEAN := TRUE;
CONSTANT c_use_phy : t_c_unb1_board_use_phy := (1, 1, sel_a_b(c_use_bg, 0, 1), 0, sel_a_b(c_use_transpose, 1, 0), 0, 0, 1);
CONSTANT c_fw_version : t_unb1_board_fw_version := (3, 8); -- firmware version x.y
CONSTANT c_tr_mesh : t_c_unb1_board_tr := c_unb1_board_tr_mesh;
CONSTANT c_dp_clk_use_pll : BOOLEAN := g_design_name="apertif_unb1_fn_bf_emu_base";
-- System -- System
SIGNAL cs_sim : STD_LOGIC; SIGNAL cs_sim : STD_LOGIC;
...@@ -145,13 +126,6 @@ ARCHITECTURE str OF apertif_unb1_fn_bf_emu IS ...@@ -145,13 +126,6 @@ ARCHITECTURE str OF apertif_unb1_fn_bf_emu IS
SIGNAL pout_debug_wave : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0); SIGNAL pout_debug_wave : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
SIGNAL pout_wdi : STD_LOGIC; SIGNAL pout_wdi : STD_LOGIC;
SIGNAL pin_intab : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL pout_intab : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
-- eth1g UDP streaming ports
SIGNAL eth1g_udp_tx_sosi_arr : t_dp_sosi_arr(c_eth_nof_udp_ports-1 DOWNTO 0);
SIGNAL eth1g_udp_tx_siso_arr : t_dp_siso_arr(c_eth_nof_udp_ports-1 DOWNTO 0);
-- Interface: 10GbE -- Interface: 10GbE
CONSTANT c_nof_10GbE_offload_streams : NATURAL := 1; CONSTANT c_nof_10GbE_offload_streams : NATURAL := 1;
CONSTANT c_pkt_len : NATURAL := 176; -- Let tr_10GbE FIFO buffer one full packet before releasing it CONSTANT c_pkt_len : NATURAL := 176; -- Let tr_10GbE FIFO buffer one full packet before releasing it
...@@ -164,56 +138,12 @@ ARCHITECTURE str OF apertif_unb1_fn_bf_emu IS ...@@ -164,56 +138,12 @@ ARCHITECTURE str OF apertif_unb1_fn_bf_emu IS
SIGNAL mdio_mdat_in_arr : STD_LOGIC_VECTOR(c_nof_10GbE_offload_streams-1 DOWNTO 0); SIGNAL mdio_mdat_in_arr : STD_LOGIC_VECTOR(c_nof_10GbE_offload_streams-1 DOWNTO 0);
SIGNAL mdio_mdat_oen_arr : STD_LOGIC_VECTOR(c_nof_10GbE_offload_streams-1 DOWNTO 0); SIGNAL mdio_mdat_oen_arr : STD_LOGIC_VECTOR(c_nof_10GbE_offload_streams-1 DOWNTO 0);
SIGNAL beamlets_qua_sosi_arr : t_dp_sosi_arr(g_bf.nof_bf_units-1 DOWNTO 0); -- 8b beamlets SIGNAL udp_offload_snk_in_arr : t_dp_sosi_arr(g_bf.nof_bf_units-1 DOWNTO 0); --FIXME: rename these to match the ones below.
SIGNAL udp_offload_snk_in_arr : t_dp_sosi_arr(g_bf.nof_bf_units-1 DOWNTO 0);
SIGNAL udp_offload_snk_out_arr : t_dp_siso_arr(g_bf.nof_bf_units-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy); SIGNAL udp_offload_snk_out_arr : t_dp_siso_arr(g_bf.nof_bf_units-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
----------------------------------------------------
-- Constants and signals for the reorder function --
--------------------------------------------------
CONSTANT c_offload_dat_w : NATURAL := 8;
CONSTANT c_use_complex : BOOLEAN := TRUE;
CONSTANT c_total_data_w : NATURAL := g_bf.nof_bf_units*c_offload_dat_w;
CONSTANT c_complex_data_w : NATURAL := c_total_data_w*c_nof_complex;
CONSTANT c_data_w : NATURAL := sel_a_b(c_use_complex, c_complex_data_w, c_total_data_w);
CONSTANT c_wr_fifo_depth : NATURAL := 256;
CONSTANT c_rd_fifo_depth : NATURAL := 256;
CONSTANT c_ddr3_mem_w : NATURAL := 256;
CONSTANT c_ena_pre_transp : BOOLEAN := TRUE;
CONSTANT c_wr_chunksize : NATURAL := 176; --240 for 6-bit or 176 for 8-bit; --g_bf.nof_weights;
CONSTANT c_rd_chunksize : NATURAL := 16; --32;
CONSTANT c_rd_nof_chunks : NATURAL := 11; --15 for 6-bit or 11 for 8-bit
CONSTANT c_rd_interval : NATURAL := c_rd_chunksize;
CONSTANT c_gapsize : NATURAL := 0;
CONSTANT c_nof_blocks : NATURAL := sel_a_b(g_sim, 16, 800000); --800000 781250);
CONSTANT c_bsn_sync_time_out : NATURAL := c_nof_blocks * g_bf.nof_weights;
CONSTANT c_reorder_seq_conf : t_reorder_seq := (c_wr_chunksize,
c_rd_chunksize,
c_rd_nof_chunks,
c_rd_interval,
c_gapsize,
c_nof_blocks);
CONSTANT c_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
-- Signals to interface with the DDR conroller and memory model.
SIGNAL ctlr_dvr_miso : t_mem_ctlr_miso;
SIGNAL ctlr_dvr_mosi : t_mem_ctlr_mosi;
SIGNAL to_mem_siso : t_dp_siso := c_dp_siso_rdy;
SIGNAL to_mem_sosi : t_dp_sosi;
SIGNAL from_mem_siso : t_dp_siso := c_dp_siso_rdy;
SIGNAL from_mem_sosi : t_dp_sosi;
SIGNAL dp_offload_tx_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0); SIGNAL dp_offload_tx_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0);
SIGNAL dp_offload_tx_src_in_arr : t_dp_siso_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0); SIGNAL dp_offload_tx_src_in_arr : t_dp_siso_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0);
SIGNAL bsn_in_sosi_arr : t_dp_sosi_arr(2-1 DOWNTO 0);
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- Memory Mapped interfaces -- Memory Mapped interfaces
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
...@@ -231,6 +161,11 @@ ARCHITECTURE str OF apertif_unb1_fn_bf_emu IS ...@@ -231,6 +161,11 @@ ARCHITECTURE str OF apertif_unb1_fn_bf_emu IS
-- PPSH -- PPSH
SIGNAL reg_ppsh_mosi : t_mem_mosi; SIGNAL reg_ppsh_mosi : t_mem_mosi;
SIGNAL reg_ppsh_miso : t_mem_miso; SIGNAL reg_ppsh_miso : t_mem_miso;
-- Block gens
SIGNAL reg_diag_bg_mosi : t_mem_mosi;
SIGNAL reg_diag_bg_miso : t_mem_miso;
SIGNAL ram_diag_bg_mosi : t_mem_mosi;
SIGNAL ram_diag_bg_miso : t_mem_miso;
-- . eth1g -- . eth1g
SIGNAL eth1g_tse_clk : STD_LOGIC; SIGNAL eth1g_tse_clk : STD_LOGIC;
SIGNAL eth1g_mm_rst : STD_LOGIC; SIGNAL eth1g_mm_rst : STD_LOGIC;
...@@ -241,68 +176,13 @@ ARCHITECTURE str OF apertif_unb1_fn_bf_emu IS ...@@ -241,68 +176,13 @@ ARCHITECTURE str OF apertif_unb1_fn_bf_emu IS
SIGNAL eth1g_reg_interrupt : STD_LOGIC; SIGNAL eth1g_reg_interrupt : STD_LOGIC;
SIGNAL eth1g_ram_mosi : t_mem_mosi := c_mem_mosi_rst; SIGNAL eth1g_ram_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL eth1g_ram_miso : t_mem_miso; SIGNAL eth1g_ram_miso : t_mem_miso;
-- . tr_mesh
SIGNAL tx_serial_2arr : t_unb1_board_mesh_sl_2arr;
SIGNAL rx_serial_2arr : t_unb1_board_mesh_sl_2arr;
-- . tr_nonbonded with diagnostics
SIGNAL reg_tr_nonbonded_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_tr_nonbonded_miso : t_mem_miso;
SIGNAL reg_diagnostics_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_diagnostics_miso : t_mem_miso;
-- . diag_data_buffer
SIGNAL ram_diag_data_buf_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL ram_diag_data_buf_miso : t_mem_miso;
SIGNAL reg_diag_data_buf_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_diag_data_buf_miso : t_mem_miso;
-- . bsn_monitor
SIGNAL reg_bsn_monitor_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_bsn_monitor_miso : t_mem_miso;
-- . block generator
SIGNAL reg_diag_bg_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_diag_bg_miso : t_mem_miso;
SIGNAL ram_diag_bg_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL ram_diag_bg_miso : t_mem_miso;
-- . beam former
SIGNAL ram_ss_ss_wide_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL ram_ss_ss_wide_miso : t_mem_miso;
SIGNAL ram_bf_weights_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL ram_bf_weights_miso : t_mem_miso;
SIGNAL ram_st_sst_bf_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL ram_st_sst_bf_miso : t_mem_miso;
SIGNAL reg_st_sst_bf_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_st_sst_bf_miso : t_mem_miso;
-- . dp_ram_from_mm for DP offload (header insertion)
SIGNAL reg_dp_ram_from_mm_mosi : t_mem_mosi;
SIGNAL reg_dp_ram_from_mm_miso : t_mem_miso := c_mem_miso_rst;
SIGNAL ram_dp_ram_from_mm_mosi : t_mem_mosi;
SIGNAL ram_dp_ram_from_mm_miso : t_mem_miso := c_mem_miso_rst;
-- . UDP offload
SIGNAL reg_dp_split_mosi : t_mem_mosi;
SIGNAL reg_dp_split_miso : t_mem_miso := c_mem_miso_rst;
SIGNAL reg_dp_pkt_merge_mosi : t_mem_mosi;
SIGNAL reg_dp_pkt_merge_miso : t_mem_miso := c_mem_miso_rst;
-- . 10GbE offload -- . 10GbE offload
SIGNAL reg_dp_offload_tx_mosi : t_mem_mosi;
SIGNAL reg_dp_offload_tx_miso : t_mem_miso;
SIGNAL reg_dp_offload_tx_hdr_dat_mosi : t_mem_mosi;
SIGNAL reg_dp_offload_tx_hdr_dat_miso : t_mem_miso;
SIGNAL reg_tr_10GbE_mosi : t_mem_mosi; SIGNAL reg_tr_10GbE_mosi : t_mem_mosi;
SIGNAL reg_tr_10GbE_miso : t_mem_miso := c_mem_miso_rst; SIGNAL reg_tr_10GbE_miso : t_mem_miso := c_mem_miso_rst;
SIGNAL reg_tr_xaui_mosi : t_mem_mosi; SIGNAL reg_tr_xaui_mosi : t_mem_mosi;
SIGNAL reg_tr_xaui_miso : t_mem_miso := c_mem_miso_rst; SIGNAL reg_tr_xaui_miso : t_mem_miso := c_mem_miso_rst;
SIGNAL reg_mdio_mosi_arr : t_mem_mosi_arr(c_unb1_board_nof_mdio-1 DOWNTO 0); SIGNAL reg_mdio_mosi_arr : t_mem_mosi_arr(c_unb1_board_nof_mdio-1 DOWNTO 0);
SIGNAL reg_mdio_miso_arr : t_mem_miso_arr(c_unb1_board_nof_mdio-1 DOWNTO 0); SIGNAL reg_mdio_miso_arr : t_mem_miso_arr(c_unb1_board_nof_mdio-1 DOWNTO 0);
-- . Pre-transpose
SIGNAL ram_ss_ss_transp_mosi : t_mem_mosi;
SIGNAL ram_ss_ss_transp_miso : t_mem_miso;
-- . DDR register map
SIGNAL reg_io_ddr_mosi : t_mem_mosi;
SIGNAL reg_io_ddr_miso : t_mem_miso;
-- . bsn_monitor
SIGNAL reg_bsn_monitor_output_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_bsn_monitor_output_miso : t_mem_miso;
BEGIN BEGIN
...@@ -379,10 +259,6 @@ BEGIN ...@@ -379,10 +259,6 @@ BEGIN
eth1g_ram_mosi => eth1g_ram_mosi, eth1g_ram_mosi => eth1g_ram_mosi,
eth1g_ram_miso => eth1g_ram_miso, eth1g_ram_miso => eth1g_ram_miso,
-- eth1g UDP streaming ports to offload BF out
udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
-- FPGA pins -- FPGA pins
-- . General -- . General
CLK => CLK, CLK => CLK,
...@@ -403,233 +279,6 @@ BEGIN ...@@ -403,233 +279,6 @@ BEGIN
ETH_SGOUT => ETH_SGOUT ETH_SGOUT => ETH_SGOUT
); );
-----------------------------------------------------------------------------
-- Node function
-----------------------------------------------------------------------------
u_node_fn_bf_emu : ENTITY work.node_apertif_unb1_fn_bf_emu
GENERIC MAP(
g_sim => g_sim,
g_use_block_gen => c_use_bg, -- TRUE overrides terminal output and feeds BG output to the BF instead.
g_use_bf => c_use_bf
)
PORT MAP(
-- System
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
dp_pps => dp_pps,
tr_mesh_clk => SB_CLK,
cal_clk => cal_rec_clk,
chip_id => this_chip_id,
-- MM interface
-- . block generator
reg_diag_bg_mosi => reg_diag_bg_mosi,
reg_diag_bg_miso => reg_diag_bg_miso,
ram_diag_bg_mosi => ram_diag_bg_mosi,
ram_diag_bg_miso => ram_diag_bg_miso,
-- . beam former
ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
ram_bf_weights_mosi => ram_bf_weights_mosi,
ram_bf_weights_miso => ram_bf_weights_miso,
ram_st_sst_bf_mosi => ram_st_sst_bf_mosi,
ram_st_sst_bf_miso => ram_st_sst_bf_miso,
reg_st_sst_bf_mosi => reg_st_sst_bf_mosi,
reg_st_sst_bf_miso => reg_st_sst_bf_miso,
-- . hdr_insert for dp offload
reg_hdr_insert_mosi => reg_dp_ram_from_mm_mosi,
ram_hdr_insert_mosi => ram_dp_ram_from_mm_mosi,
-- . dp_split for dp offload
reg_dp_split_mosi => reg_dp_split_mosi,
reg_dp_split_miso => reg_dp_split_miso,
reg_dp_pkt_merge_mosi => reg_dp_pkt_merge_mosi,
reg_dp_pkt_merge_miso => reg_dp_pkt_merge_miso,
-- . tr_nonbonded
reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
reg_diagnostics_mosi => reg_diagnostics_mosi,
reg_diagnostics_miso => reg_diagnostics_miso,
-- . diag_data_buffer
ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
ram_diag_data_buf_miso => ram_diag_data_buf_miso,
reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
reg_diag_data_buf_miso => reg_diag_data_buf_miso,
-- . bsn_monitor
reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
reg_bsn_monitor_miso => reg_bsn_monitor_miso,
-- ST interface, BF beamlets out
beamlets_bst_sosi_arr => OPEN, -- 16b beamlets; for 1GbE a selection can be offloaded via bf_out_offload_tx_sosi_arr.
beamlets_qua_sosi_arr => beamlets_qua_sosi_arr, -- 8b beamlets; for 10GbE offload
-- 1GbE offload
bf_out_offload_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
bf_out_offload_tx_siso_arr => eth1g_udp_tx_siso_arr,
-- Mesh interface
tx_serial_2arr => tx_serial_2arr,
rx_serial_2arr => rx_serial_2arr
);
gen_no_transpose : IF c_use_transpose = FALSE GENERATE
dp_rst <= ctrl_dp_rst;
dp_clk <= ctrl_dp_clk;
udp_offload_snk_in_arr <= beamlets_qua_sosi_arr;
END GENERATE;
gen_transpose : IF c_use_transpose = TRUE GENERATE
----------------------------------------------------------------------------
-- Transpose function
----------------------------------------------------------------------------
u_transpose: ENTITY reorder_lib.reorder_transpose
GENERIC MAP(
g_nof_streams => g_bf.nof_bf_units,
g_in_dat_w => c_offload_dat_w,
g_frame_size_in => g_bf.nof_weights, -- 256
g_frame_size_out => c_pkt_len, -- 176
g_use_complex => c_use_complex,
g_mem_dat_w => c_ddr3_mem_w,
g_ena_pre_transp => c_ena_pre_transp,
g_reorder_seq => c_reorder_seq_conf
)
PORT MAP (
mm_rst => mm_rst,
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
-- ST sink
snk_out_arr => OPEN,
snk_in_arr => beamlets_qua_sosi_arr,
-- ST source
src_in_arr => udp_offload_snk_out_arr,
src_out_arr => udp_offload_snk_in_arr,
ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
-- Control interface to the external memory
dvr_miso => ctlr_dvr_miso,
dvr_mosi => ctlr_dvr_mosi,
-- Data interface to the external memory
to_mem_src_out => to_mem_sosi,
to_mem_src_in => to_mem_siso,
from_mem_snk_in => from_mem_sosi,
from_mem_snk_out => from_mem_siso
);
u_areset_ddr_ref_rst : ENTITY common_lib.common_areset
GENERIC MAP(
g_rst_level => '1',
g_delay_len => 40
)
PORT MAP(
clk => CLK,
in_rst => '0',
out_rst => ddr_ref_rst
);
u_ddr_mem_ctrl : ENTITY io_ddr_lib.io_ddr
GENERIC MAP(
g_sim_model => g_sim_model,
g_technology => c_tech_select_default,
g_tech_ddr => c_tech_ddr,
g_cross_domain_dvr_ctlr => FALSE,
g_wr_data_w => c_data_w,
g_wr_fifo_depth => c_wr_fifo_depth,
g_rd_fifo_depth => c_rd_fifo_depth,
g_rd_data_w => c_data_w,
g_wr_flush_mode => "SYN",
g_wr_flush_use_channel => FALSE,
g_wr_flush_start_channel => 0,
g_wr_flush_nof_channels => 1
)
PORT MAP (
-- DDR reference clock
ctlr_ref_clk => CLK,
ctlr_ref_rst => ddr_ref_rst,
-- DDR controller clock domain
ctlr_clk_out => dp_clk,
ctlr_rst_out => dp_rst,
ctlr_clk_in => dp_clk,
ctlr_rst_in => dp_rst,
-- MM clock + reset
mm_rst => mm_rst,
mm_clk => mm_clk,
-- MM register map for DDR controller status info
reg_io_ddr_mosi => reg_io_ddr_mosi,
reg_io_ddr_miso => reg_io_ddr_miso,
-- Driver clock domain
dvr_clk => dp_clk,
dvr_rst => dp_rst,
dvr_miso => ctlr_dvr_miso,
dvr_mosi => ctlr_dvr_mosi,
-- Write FIFO clock domain
wr_clk => dp_clk,
wr_rst => dp_rst,
wr_fifo_usedw => OPEN,
wr_sosi => to_mem_sosi,
wr_siso => to_mem_siso,
-- Read FIFO clock domain
rd_clk => dp_clk,
rd_rst => dp_rst,
rd_fifo_usedw => OPEN,
rd_sosi => from_mem_sosi,
rd_siso => from_mem_siso,
phy3_in => MB_I_IN,
phy3_io => MB_I_IO,
phy3_ou => MB_I_OU
);
END GENERATE;
-----------------------------------------------------------------------------
-- Mesh I/O
-----------------------------------------------------------------------------
no_tr_mesh : IF c_use_phy.tr_mesh=0 GENERATE
rx_serial_2arr <= (OTHERS=>(OTHERS=>'0'));
END GENERATE;
gen_tr_mesh : IF c_use_phy.tr_mesh/=0 GENERATE
u_mesh_io : ENTITY unb1_board_lib.unb1_board_mesh_io
GENERIC MAP (
g_bus_w => c_tr_mesh.bus_w
)
PORT MAP (
tx_serial_2arr => tx_serial_2arr,
rx_serial_2arr => rx_serial_2arr,
-- Serial I/O
FN_BN_0_TX => FN_BN_0_TX,
FN_BN_0_RX => FN_BN_0_RX,
FN_BN_1_TX => FN_BN_1_TX,
FN_BN_1_RX => FN_BN_1_RX,
FN_BN_2_TX => FN_BN_2_TX,
FN_BN_2_RX => FN_BN_2_RX,
FN_BN_3_TX => FN_BN_3_TX,
FN_BN_3_RX => FN_BN_3_RX
);
END GENERATE;
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- Interface : 10GbE -- Interface : 10GbE
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
...@@ -726,36 +375,10 @@ BEGIN ...@@ -726,36 +375,10 @@ BEGIN
SI_FN_3_CNTRL => SI_FN_3_CNTRL SI_FN_3_CNTRL => SI_FN_3_CNTRL
); );
u_bsn_monitor_align : ENTITY dp_lib.mms_dp_bsn_monitor
GENERIC MAP (
g_nof_streams => 2,
g_cross_clock_domain => TRUE,
g_sync_timeout => c_bsn_sync_time_out,
g_bsn_w => c_dp_stream_bsn_w,
g_cnt_sop_w => c_word_w,
g_cnt_valid_w => c_word_w,
g_log_first_bsn => TRUE
)
PORT MAP (
-- Memory-mapped clock domain
mm_rst => mm_rst,
mm_clk => mm_clk,
reg_mosi => reg_bsn_monitor_output_mosi,
reg_miso => reg_bsn_monitor_output_miso,
-- Streaming clock domain
dp_rst => dp_rst,
dp_clk => dp_clk,
in_siso_arr => (OTHERS => c_dp_siso_rdy),
in_sosi_arr => bsn_in_sosi_arr(1 DOWNTO 0)
);
bsn_in_sosi_arr(0) <= udp_offload_snk_in_arr(0);
bsn_in_sosi_arr(1) <= dp_offload_tx_src_out_arr(0);
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- DP offload TX : BF out -> 10GbE -- DP offload TX : BF out -> 10GbE
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
u_fn_bf_emu_udp_offload : ENTITY work.apertif_unb1_fn_bf_emu_udp_offload u_fn_beamformer_udp_offload : ENTITY work.apertif_unb1_fn_beamformer_udp_offload
PORT MAP ( PORT MAP (
mm_rst => mm_rst, mm_rst => mm_rst,
mm_clk => mm_clk, mm_clk => mm_clk,
...@@ -770,10 +393,10 @@ BEGIN ...@@ -770,10 +393,10 @@ BEGIN
ID => ID, ID => ID,
reg_dp_offload_tx_mosi => reg_dp_offload_tx_mosi, reg_dp_offload_tx_mosi => c_mem_mosi_rst,
reg_dp_offload_tx_miso => reg_dp_offload_tx_miso, reg_dp_offload_tx_miso => OPEN,
reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi, reg_dp_offload_tx_hdr_dat_mosi => c_mem_mosi_rst,
reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso reg_dp_offload_tx_hdr_dat_miso => OPEN
); );
u_mmm : ENTITY work.mmm_apertif_unb1_fn_bf_emu u_mmm : ENTITY work.mmm_apertif_unb1_fn_bf_emu
...@@ -781,9 +404,7 @@ BEGIN ...@@ -781,9 +404,7 @@ BEGIN
-- General -- General
g_sim => g_sim, g_sim => g_sim,
g_sim_unb_nr => g_sim_unb_nr, g_sim_unb_nr => g_sim_unb_nr,
g_sim_node_nr => g_sim_node_nr, g_sim_node_nr => g_sim_node_nr
g_bf => g_bf,
g_reorder_seq => c_reorder_seq_conf
) )
PORT MAP ( PORT MAP (
xo_clk => xo_clk, xo_clk => xo_clk,
...@@ -815,57 +436,12 @@ BEGIN ...@@ -815,57 +436,12 @@ BEGIN
reg_ppsh_mosi => reg_ppsh_mosi, reg_ppsh_mosi => reg_ppsh_mosi,
reg_ppsh_miso => reg_ppsh_miso, reg_ppsh_miso => reg_ppsh_miso,
-- Diagnostics
reg_diagnostics_mosi => reg_diagnostics_mosi,
reg_diagnostics_miso => reg_diagnostics_miso,
-- . tr_nonbonded with diagnostics
reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
-- . diag_data_buffer
ram_diag_data_buf_mosi => ram_diag_data_buf_mosi,
ram_diag_data_buf_miso => ram_diag_data_buf_miso,
reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
reg_diag_data_buf_miso => reg_diag_data_buf_miso,
-- . bsn_monitor -- Block gens
reg_bsn_monitor_mosi => reg_bsn_monitor_mosi,
reg_bsn_monitor_miso => reg_bsn_monitor_miso,
-- . beamformer
ram_st_sst_bf_mosi => ram_st_sst_bf_mosi,
ram_st_sst_bf_miso => ram_st_sst_bf_miso,
reg_st_sst_bf_mosi => reg_st_sst_bf_mosi,
reg_st_sst_bf_miso => reg_st_sst_bf_miso,
ram_ss_ss_wide_mosi => ram_ss_ss_wide_mosi,
ram_ss_ss_wide_miso => ram_ss_ss_wide_miso,
ram_bf_weights_mosi => ram_bf_weights_mosi,
ram_bf_weights_miso => ram_bf_weights_miso,
reg_diag_bg_mosi => reg_diag_bg_mosi,
reg_diag_bg_miso => reg_diag_bg_miso,
ram_diag_bg_mosi => ram_diag_bg_mosi, ram_diag_bg_mosi => ram_diag_bg_mosi,
ram_diag_bg_miso => ram_diag_bg_miso, ram_diag_bg_miso => ram_diag_bg_miso,
reg_diag_bg_mosi => reg_diag_bg_mosi,
-- . dp_ram_from_mm for DP offload (header insertion) reg_diag_bg_miso => reg_diag_bg_miso,
reg_dp_ram_from_mm_mosi => reg_dp_ram_from_mm_mosi,
reg_dp_ram_from_mm_miso => reg_dp_ram_from_mm_miso,
ram_dp_ram_from_mm_mosi => ram_dp_ram_from_mm_mosi,
ram_dp_ram_from_mm_miso => ram_dp_ram_from_mm_miso,
-- . UDP offload
reg_dp_split_mosi => reg_dp_split_mosi,
reg_dp_split_miso => reg_dp_split_miso,
reg_dp_pkt_merge_mosi => reg_dp_pkt_merge_mosi,
reg_dp_pkt_merge_miso => reg_dp_pkt_merge_miso,
-- . 10GbE offload
reg_dp_offload_tx_mosi => reg_dp_offload_tx_mosi,
reg_dp_offload_tx_miso => reg_dp_offload_tx_miso,
reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
reg_tr_10GbE_mosi => reg_tr_10GbE_mosi, reg_tr_10GbE_mosi => reg_tr_10GbE_mosi,
reg_tr_10GbE_miso => reg_tr_10GbE_miso, reg_tr_10GbE_miso => reg_tr_10GbE_miso,
...@@ -876,18 +452,6 @@ BEGIN ...@@ -876,18 +452,6 @@ BEGIN
reg_tr_xaui_mosi => reg_tr_xaui_mosi, reg_tr_xaui_mosi => reg_tr_xaui_mosi,
reg_tr_xaui_miso => reg_tr_xaui_miso, reg_tr_xaui_miso => reg_tr_xaui_miso,
-- . Pre-transpose
ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
-- . DDR register map
reg_io_ddr_mosi => reg_io_ddr_mosi,
reg_io_ddr_miso => reg_io_ddr_miso,
-- . bsn_monitor_output
reg_bsn_monitor_output_mosi => reg_bsn_monitor_output_mosi,
reg_bsn_monitor_output_miso => reg_bsn_monitor_output_miso,
-- eth1g -- eth1g
eth1g_tse_clk => eth1g_tse_clk, eth1g_tse_clk => eth1g_tse_clk,
eth1g_mm_rst => eth1g_mm_rst, eth1g_mm_rst => eth1g_mm_rst,
......
applications/apertif/designs/apertif_unb1_fn_bf_emu/src/vhdl/mmm_apertif_unb1_fn_bf_emu.vhd
+ 15
− 302
View file @ f248d57e
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- --
-- Copyright (C) 2013 -- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
-- --
...@@ -48,9 +48,7 @@ ENTITY mmm_apertif_unb1_fn_bf_emu IS ...@@ -48,9 +48,7 @@ ENTITY mmm_apertif_unb1_fn_bf_emu IS
g_sim : BOOLEAN := FALSE; --FALSE: use SOPC; TRUE: use mm_file I/O g_sim : BOOLEAN := FALSE; --FALSE: use SOPC; TRUE: use mm_file I/O
g_sim_unb_nr : NATURAL := 0; g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0; g_sim_node_nr : NATURAL := 0;
g_tech_select : INTEGER := c_tech_select_default; g_tech_select : INTEGER := c_tech_select_default
g_bf : t_c_bf := c_bf;
g_reorder_seq : t_reorder_seq := c_reorder_seq
); );
PORT ( PORT (
xo_clk : IN STD_LOGIC; xo_clk : IN STD_LOGIC;
...@@ -82,57 +80,13 @@ ENTITY mmm_apertif_unb1_fn_bf_emu IS ...@@ -82,57 +80,13 @@ ENTITY mmm_apertif_unb1_fn_bf_emu IS
reg_ppsh_mosi : OUT t_mem_mosi; reg_ppsh_mosi : OUT t_mem_mosi;
reg_ppsh_miso : IN t_mem_miso; reg_ppsh_miso : IN t_mem_miso;
-- Diagnostics -- Block gens
reg_diagnostics_mosi : OUT t_mem_mosi; ram_diag_bg_mosi : OUT t_mem_mosi;
reg_diagnostics_miso : IN t_mem_miso;
-- . tr_nonbonded with diagnostics
reg_tr_nonbonded_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
reg_tr_nonbonded_miso : IN t_mem_miso;
-- . diag_data_buffer
ram_diag_data_buf_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
ram_diag_data_buf_miso : IN t_mem_miso;
reg_diag_data_buf_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
reg_diag_data_buf_miso : IN t_mem_miso;
-- . bsn_monitor
reg_bsn_monitor_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
reg_bsn_monitor_miso : IN t_mem_miso;
-- . beamformer
ram_st_sst_bf_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
ram_st_sst_bf_miso : IN t_mem_miso;
reg_st_sst_bf_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
reg_st_sst_bf_miso : IN t_mem_miso;
ram_ss_ss_wide_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
ram_ss_ss_wide_miso : IN t_mem_miso;
ram_bf_weights_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
ram_bf_weights_miso : IN t_mem_miso;
reg_diag_bg_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
reg_diag_bg_miso : IN t_mem_miso;
ram_diag_bg_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
ram_diag_bg_miso : IN t_mem_miso; ram_diag_bg_miso : IN t_mem_miso;
reg_diag_bg_mosi : OUT t_mem_mosi;
-- . dp_ram_from_mm for DP offload (header insertion) reg_diag_bg_miso : IN t_mem_miso;
reg_dp_ram_from_mm_mosi : OUT t_mem_mosi;
reg_dp_ram_from_mm_miso : IN t_mem_miso := c_mem_miso_rst;
ram_dp_ram_from_mm_mosi : OUT t_mem_mosi;
ram_dp_ram_from_mm_miso : IN t_mem_miso := c_mem_miso_rst;
-- . UDP offload
reg_dp_split_mosi : OUT t_mem_mosi;
reg_dp_split_miso : IN t_mem_miso := c_mem_miso_rst;
reg_dp_pkt_merge_mosi : OUT t_mem_mosi;
reg_dp_pkt_merge_miso : IN t_mem_miso := c_mem_miso_rst;
-- . 10GbE offload -- . 10GbE offload
reg_dp_offload_tx_mosi : OUT t_mem_mosi;
reg_dp_offload_tx_miso : IN t_mem_miso;
reg_dp_offload_tx_hdr_dat_mosi : OUT t_mem_mosi;
reg_dp_offload_tx_hdr_dat_miso : IN t_mem_miso;
reg_tr_10GbE_mosi : OUT t_mem_mosi; reg_tr_10GbE_mosi : OUT t_mem_mosi;
reg_tr_10GbE_miso : IN t_mem_miso; reg_tr_10GbE_miso : IN t_mem_miso;
...@@ -142,17 +96,6 @@ ENTITY mmm_apertif_unb1_fn_bf_emu IS ...@@ -142,17 +96,6 @@ ENTITY mmm_apertif_unb1_fn_bf_emu IS
reg_tr_xaui_mosi : OUT t_mem_mosi; reg_tr_xaui_mosi : OUT t_mem_mosi;
reg_tr_xaui_miso : IN t_mem_miso := c_mem_miso_rst; reg_tr_xaui_miso : IN t_mem_miso := c_mem_miso_rst;
ram_ss_ss_transp_mosi : OUT t_mem_mosi;
ram_ss_ss_transp_miso : IN t_mem_miso := c_mem_miso_rst;
-- IO DDR register map
reg_io_ddr_mosi : OUT t_mem_mosi;
reg_io_ddr_miso : IN t_mem_miso := c_mem_miso_rst;
-- . bsn_monitor_output
reg_bsn_monitor_output_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
reg_bsn_monitor_output_miso : IN t_mem_miso;
-- eth1g -- eth1g
eth1g_tse_clk : OUT STD_LOGIC; eth1g_tse_clk : OUT STD_LOGIC;
eth1g_mm_rst : OUT STD_LOGIC; eth1g_mm_rst : OUT STD_LOGIC;
...@@ -170,33 +113,13 @@ END mmm_apertif_unb1_fn_bf_emu; ...@@ -170,33 +113,13 @@ END mmm_apertif_unb1_fn_bf_emu;
ARCHITECTURE str OF mmm_apertif_unb1_fn_bf_emu IS ARCHITECTURE str OF mmm_apertif_unb1_fn_bf_emu IS
-- Custom register widths -- Block generators
CONSTANT c_bg_diag_wave_period : POSITIVE := 4; -- . 4 instances, one for each BF unit.
CONSTANT c_ram_st_sst_bf_addr_w : NATURAL := ceil_log2(c_bf_max_nof_bf_units*g_bf.stat_data_sz*g_bf.nof_weights*c_nof_complex); -- . Block size/instance: 256 beamlets
CONSTANT c_reg_st_sst_bf_addr_w : NATURAL := ceil_log2(c_bf_max_nof_bf_units)*2; -- . Data width: 16b complex (2*8b).
CONSTANT c_ram_ss_ss_wide_addr_w : NATURAL := ceil_log2(c_bf_max_nof_bf_units*g_bf.nof_weights*g_bf.nof_signal_paths); CONSTANT c_ram_diag_bg_addr_w : NATURAL := ceil_log2(4*256);
CONSTANT c_ram_bf_weights_addr_w : NATURAL := ceil_log2(c_bf_max_nof_bf_units*g_bf.nof_signal_paths*g_bf.nof_weights);
CONSTANT c_ram_diag_bg_addr_w : NATURAL := ceil_log2(c_bg_diag_wave_period) + ceil_log2(g_bf.nof_subbands*g_bf.nof_signal_paths/g_bf.nof_input_streams)+ceil_log2(g_bf.nof_input_streams);
CONSTANT c_dp_ram_mm_nof_words : NATURAL := c_network_total_header_32b_nof_words * (c_tech_tse_data_w/c_word_w);
CONSTANT c_dp_ram_mm_adr_w : NATURAL := ceil_log2(g_bf.nof_bf_units * pow2(ceil_log2(c_dp_ram_mm_nof_words)));
CONSTANT c_reg_bsn_monitor_output_adr_w : NATURAL := 5;
CONSTANT c_ram_ss_ss_transp_addr_w : NATURAL := ceil_log2(g_reorder_seq.rd_chunksize*g_bf.nof_weights*2);
CONSTANT c_mm_reg_io_ddr_addr_w : NATURAL := ceil_log2(16);
CONSTANT c_dp_reg_mm_nof_words : NATURAL := 1;
CONSTANT c_dp_reg_mm_adr_w : NATURAL := ceil_log2(g_bf.nof_bf_units * pow2(ceil_log2(c_dp_reg_mm_nof_words)));
CONSTANT c_reg_dp_split_nof_words : NATURAL := 1;
CONSTANT c_reg_dp_split_adr_w : NATURAL := ceil_log2(g_bf.nof_bf_units * pow2(ceil_log2(c_reg_dp_split_nof_words)));
CONSTANT c_reg_dp_pkt_merge_nof_words : NATURAL := 1;
CONSTANT c_reg_dp_pkt_merge_adr_w : NATURAL := ceil_log2(c_eth_nof_udp_ports * pow2(ceil_log2(c_reg_dp_pkt_merge_nof_words)));
-- 10GbE offload -- 10GbE offload
CONSTANT c_reg_dp_offload_tx_adr_w : NATURAL := 1;
CONSTANT c_reg_dp_offload_tx_hdr_dat_nof_words : NATURAL := field_nof_words(c_apertif_udp_offload_hdr_field_arr, c_word_w); -- = 26 32b words
CONSTANT c_reg_dp_offload_tx_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_hdr_dat_nof_words); -- = 5
CONSTANT c_reg_dp_offload_tx_hdr_ovr_nof_words : NATURAL := c_apertif_udp_offload_hdr_field_arr'LENGTH; -- = 23 override bits; one for each field; each bit in its own 32b register.
CONSTANT c_reg_dp_offload_tx_hdr_ovr_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_hdr_ovr_nof_words); -- = 5
CONSTANT c_reg_tr_10GbE_adr_w : NATURAL := func_tech_mac_10g_csr_addr_w(g_tech_select); CONSTANT c_reg_tr_10GbE_adr_w : NATURAL := func_tech_mac_10g_csr_addr_w(g_tech_select);
CONSTANT c_xaui_mosi_addr_w : NATURAL := 9; --2^9 = range of 512 addresses CONSTANT c_xaui_mosi_addr_w : NATURAL := 9; --2^9 = range of 512 addresses
CONSTANT c_max_nof_xaui_inst : NATURAL := 4; CONSTANT c_max_nof_xaui_inst : NATURAL := 4;
...@@ -284,63 +207,15 @@ BEGIN ...@@ -284,63 +207,15 @@ BEGIN
u_mm_file_reg_ppsh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS") u_mm_file_reg_ppsh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
PORT MAP(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso ); PORT MAP(mm_rst, i_mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
u_mm_file_reg_diagnostics : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAGNOSTICS")
PORT MAP(mm_rst, i_mm_clk, reg_diagnostics_mosi, reg_diagnostics_miso );
u_mm_file_reg_tr_nonbonded : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_NONBONDED")
PORT MAP(mm_rst, i_mm_clk, reg_tr_nonbonded_mosi, reg_tr_nonbonded_miso );
u_mm_file_ram_diag_data_buf : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER")
PORT MAP(mm_rst, i_mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso);
u_mm_file_reg_diag_data_buf : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_DATA_BUFFER")
PORT MAP(mm_rst, i_mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso);
u_mm_file_reg_bsn_monitor : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR")
PORT MAP(mm_rst, i_mm_clk, reg_bsn_monitor_mosi, reg_bsn_monitor_miso );
u_mm_file_ram_st_sst_bf : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_SST")
PORT MAP(mm_rst, i_mm_clk, ram_st_sst_bf_mosi, ram_st_sst_bf_miso );
u_mm_file_reg_st_sst_bf : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_ST_SST")
PORT MAP(mm_rst, i_mm_clk, reg_st_sst_bf_mosi, reg_st_sst_bf_miso );
u_mm_file_ram_ss_ss_wide : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE")
PORT MAP(mm_rst, i_mm_clk, ram_ss_ss_wide_mosi, ram_ss_ss_wide_miso );
u_mm_file_ram_bf_weights : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_BF_WEIGHTS")
PORT MAP(mm_rst, i_mm_clk, ram_bf_weights_mosi, ram_bf_weights_miso );
u_mm_file_reg_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG") u_mm_file_reg_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG")
PORT MAP(mm_rst, i_mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso ); PORT MAP(mm_rst, i_mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso );
u_mm_file_ram_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG") u_mm_file_ram_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
PORT MAP(mm_rst, i_mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso ); PORT MAP(mm_rst, i_mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso );
u_mm_file_reg_dp_ram_from_mm : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_RAM_FROM_MM")
PORT MAP(mm_rst, i_mm_clk, reg_dp_ram_from_mm_mosi, reg_dp_ram_from_mm_miso );
u_mm_file_ram_dp_ram_from_mm : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DP_RAM_FROM_MM")
PORT MAP(mm_rst, i_mm_clk, ram_dp_ram_from_mm_mosi, ram_dp_ram_from_mm_miso );
u_mm_file_reg_dp_split : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SPLIT")
PORT MAP(mm_rst, i_mm_clk, reg_dp_split_mosi, reg_dp_split_miso );
u_mm_file_reg_dp_pkt_merge : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_PKT_MERGE")
PORT MAP(mm_rst, i_mm_clk, reg_dp_pkt_merge_mosi, reg_dp_pkt_merge_miso );
u_mm_file_ram_ss_ss_transp : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SS_SS_WIDE_TRANSP")
PORT MAP(mm_rst, i_mm_clk, ram_ss_ss_transp_mosi, ram_ss_ss_transp_miso );
u_mm_file_reg_io_ddr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR")
PORT MAP(mm_rst, i_mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso);
u_mm_file_reg_tr_xaui_mosi : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_XAUI") u_mm_file_reg_tr_xaui_mosi : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_XAUI")
PORT MAP(mm_rst, i_mm_clk, reg_tr_xaui_mosi, reg_tr_xaui_miso); PORT MAP(mm_rst, i_mm_clk, reg_tr_xaui_mosi, reg_tr_xaui_miso);
u_mm_file_reg_bsn_monitor_output : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_OUTPUT")
PORT MAP(mm_rst, i_mm_clk, reg_bsn_monitor_output_mosi, reg_bsn_monitor_output_miso );
u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG") u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
PORT MAP(mm_rst, i_mm_clk, i_eth1g_reg_mosi, eth1g_reg_miso ); PORT MAP(mm_rst, i_mm_clk, i_eth1g_reg_mosi, eth1g_reg_miso );
...@@ -432,60 +307,6 @@ BEGIN ...@@ -432,60 +307,6 @@ BEGIN
coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr, coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w-1 DOWNTO 0), coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_tr_nonbonded_mesh
coe_address_export_from_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_tr_nonbonded_adr_w-1 DOWNTO 0),
coe_clk_export_from_the_reg_tr_nonbonded_mesh => OPEN,
coe_read_export_from_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_mosi.rd,
coe_readdata_export_to_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_miso.rddata(c_word_w-1 DOWNTO 0),
coe_reset_export_from_the_reg_tr_nonbonded_mesh => OPEN,
coe_write_export_from_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_mosi.wr,
coe_writedata_export_from_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_diagnostics_mesh
coe_address_export_from_the_reg_diagnostics_mesh => reg_diagnostics_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diagnostics_adr_w-1 DOWNTO 0),
coe_clk_export_from_the_reg_diagnostics_mesh => OPEN,
coe_read_export_from_the_reg_diagnostics_mesh => reg_diagnostics_mosi.rd,
coe_readdata_export_to_the_reg_diagnostics_mesh => reg_diagnostics_miso.rddata(c_word_w-1 DOWNTO 0),
coe_reset_export_from_the_reg_diagnostics_mesh => OPEN,
coe_write_export_from_the_reg_diagnostics_mesh => reg_diagnostics_mosi.wr,
coe_writedata_export_from_the_reg_diagnostics_mesh => reg_diagnostics_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_ram_diag_data_buffer
coe_address_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.ram_diag_db_adr_w-1 DOWNTO 0),
coe_clk_export_from_the_ram_diag_data_buffer => OPEN,
coe_read_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.rd,
coe_readdata_export_to_the_ram_diag_data_buffer => ram_diag_data_buf_miso.rddata(c_word_w-1 DOWNTO 0),
coe_reset_export_from_the_ram_diag_data_buffer => OPEN,
coe_write_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wr,
coe_writedata_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_diag_data_buffer
coe_address_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_db_adr_w-1 DOWNTO 0),
coe_clk_export_from_the_reg_diag_data_buffer => OPEN,
coe_read_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.rd,
coe_readdata_export_to_the_reg_diag_data_buffer => reg_diag_data_buf_miso.rddata(c_word_w-1 DOWNTO 0),
coe_reset_export_from_the_reg_diag_data_buffer => OPEN,
coe_write_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wr,
coe_writedata_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_bsn_monitor
coe_address_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_bsn_monitor_adr_w-1 DOWNTO 0),
coe_clk_export_from_the_reg_bsn_monitor => OPEN,
coe_read_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.rd,
coe_readdata_export_to_the_reg_bsn_monitor => reg_bsn_monitor_miso.rddata(c_word_w-1 DOWNTO 0),
coe_reset_export_from_the_reg_bsn_monitor => OPEN,
coe_write_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wr,
coe_writedata_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_bsn_monitor_output
coe_address_export_from_the_reg_bsn_monitor_output => reg_bsn_monitor_output_mosi.address(c_reg_bsn_monitor_output_adr_w-1 DOWNTO 0),
coe_clk_export_from_the_reg_bsn_monitor_output => OPEN,
coe_read_export_from_the_reg_bsn_monitor_output => reg_bsn_monitor_output_mosi.rd,
coe_readdata_export_to_the_reg_bsn_monitor_output => reg_bsn_monitor_output_miso.rddata(c_word_w-1 DOWNTO 0),
coe_reset_export_from_the_reg_bsn_monitor_output => OPEN,
coe_write_export_from_the_reg_bsn_monitor_output => reg_bsn_monitor_output_mosi.wr,
coe_writedata_export_from_the_reg_bsn_monitor_output => reg_bsn_monitor_output_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_pio_debug_wave -- the_pio_debug_wave
out_port_from_the_pio_debug_wave => OPEN, out_port_from_the_pio_debug_wave => OPEN,
...@@ -528,60 +349,6 @@ BEGIN ...@@ -528,60 +349,6 @@ BEGIN
coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr, coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0), coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_ram_st_sst
coe_address_export_from_the_ram_st_sst => ram_st_sst_bf_mosi.address(c_ram_st_sst_bf_addr_w-1 DOWNTO 0),
coe_clk_export_from_the_ram_st_sst => OPEN,
coe_read_export_from_the_ram_st_sst => ram_st_sst_bf_mosi.rd,
coe_readdata_export_to_the_ram_st_sst => ram_st_sst_bf_miso.rddata(c_word_w-1 DOWNTO 0),
coe_reset_export_from_the_ram_st_sst => OPEN,
coe_write_export_from_the_ram_st_sst => ram_st_sst_bf_mosi.wr,
coe_writedata_export_from_the_ram_st_sst => ram_st_sst_bf_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_st_sst
coe_address_export_from_the_reg_st_sst => reg_st_sst_bf_mosi.address(c_reg_st_sst_bf_addr_w-1 DOWNTO 0),
coe_clk_export_from_the_reg_st_sst => OPEN,
coe_read_export_from_the_reg_st_sst => reg_st_sst_bf_mosi.rd,
coe_readdata_export_to_the_reg_st_sst => reg_st_sst_bf_miso.rddata(c_word_w-1 DOWNTO 0),
coe_reset_export_from_the_reg_st_sst => OPEN,
coe_write_export_from_the_reg_st_sst => reg_st_sst_bf_mosi.wr,
coe_writedata_export_from_the_reg_st_sst => reg_st_sst_bf_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_ram_ss_ss_wide
coe_address_export_from_the_ram_ss_ss_wide => ram_ss_ss_wide_mosi.address(c_ram_ss_ss_wide_addr_w-1 DOWNTO 0),
coe_clk_export_from_the_ram_ss_ss_wide => OPEN,
coe_read_export_from_the_ram_ss_ss_wide => ram_ss_ss_wide_mosi.rd,
coe_readdata_export_to_the_ram_ss_ss_wide => ram_ss_ss_wide_miso.rddata(c_word_w-1 DOWNTO 0),
coe_reset_export_from_the_ram_ss_ss_wide => OPEN,
coe_write_export_from_the_ram_ss_ss_wide => ram_ss_ss_wide_mosi.wr,
coe_writedata_export_from_the_ram_ss_ss_wide => ram_ss_ss_wide_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_ram_ss_ss_transpose
coe_address_export_from_the_ram_ss_ss_transp => ram_ss_ss_transp_mosi.address(c_ram_ss_ss_transp_addr_w-1 DOWNTO 0),
coe_clk_export_from_the_ram_ss_ss_transp => OPEN,
coe_read_export_from_the_ram_ss_ss_transp => ram_ss_ss_transp_mosi.rd,
coe_readdata_export_to_the_ram_ss_ss_transp => ram_ss_ss_transp_miso.rddata(c_word_w-1 DOWNTO 0),
coe_reset_export_from_the_ram_ss_ss_transp => OPEN,
coe_write_export_from_the_ram_ss_ss_transp => ram_ss_ss_transp_mosi.wr,
coe_writedata_export_from_the_ram_ss_ss_transp => ram_ss_ss_transp_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_io_ddr
coe_address_export_from_the_reg_io_ddr => reg_io_ddr_mosi.address(c_mm_reg_io_ddr_addr_w-1 DOWNTO 0),
coe_clk_export_from_the_reg_io_ddr => OPEN,
coe_read_export_from_the_reg_io_ddr => reg_io_ddr_mosi.rd,
coe_readdata_export_to_the_reg_io_ddr => reg_io_ddr_miso.rddata(c_word_w-1 DOWNTO 0),
coe_reset_export_from_the_reg_io_ddr => OPEN,
coe_write_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wr,
coe_writedata_export_from_the_reg_io_ddr => reg_io_ddr_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_ram_bf_weights
coe_address_export_from_the_ram_bf_weights => ram_bf_weights_mosi.address(c_ram_bf_weights_addr_w-1 DOWNTO 0),
coe_clk_export_from_the_ram_bf_weights => OPEN,
coe_read_export_from_the_ram_bf_weights => ram_bf_weights_mosi.rd,
coe_readdata_export_to_the_ram_bf_weights => ram_bf_weights_miso.rddata(c_word_w-1 DOWNTO 0),
coe_reset_export_from_the_ram_bf_weights => OPEN,
coe_write_export_from_the_ram_bf_weights => ram_bf_weights_mosi.wr,
coe_writedata_export_from_the_ram_bf_weights => ram_bf_weights_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_bg_diag_bg -- the_reg_bg_diag_bg
coe_address_export_from_the_reg_diag_bg => reg_diag_bg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_bg_adr_w-1 DOWNTO 0), coe_address_export_from_the_reg_diag_bg => reg_diag_bg_mosi.address(c_unb1_board_peripherals_mm_reg_default.reg_diag_bg_adr_w-1 DOWNTO 0),
coe_clk_export_from_the_reg_diag_bg => OPEN, coe_clk_export_from_the_reg_diag_bg => OPEN,
...@@ -600,60 +367,6 @@ BEGIN ...@@ -600,60 +367,6 @@ BEGIN
coe_write_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wr, coe_write_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wr,
coe_writedata_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wrdata(c_word_w-1 DOWNTO 0), coe_writedata_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_dp_ram_from_mm
coe_clk_export_from_the_reg_dp_ram_from_mm => OPEN,
coe_reset_export_from_the_reg_dp_ram_from_mm => OPEN,
coe_address_export_from_the_reg_dp_ram_from_mm => reg_dp_ram_from_mm_mosi.address(c_dp_reg_mm_adr_w-1 DOWNTO 0),
coe_read_export_from_the_reg_dp_ram_from_mm => reg_dp_ram_from_mm_mosi.rd,
coe_readdata_export_to_the_reg_dp_ram_from_mm => reg_dp_ram_from_mm_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_dp_ram_from_mm => reg_dp_ram_from_mm_mosi.wr,
coe_writedata_export_from_the_reg_dp_ram_from_mm => reg_dp_ram_from_mm_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_ram_dp_ram_from_mm
coe_clk_export_from_the_ram_dp_ram_from_mm => OPEN,
coe_reset_export_from_the_ram_dp_ram_from_mm => OPEN,
coe_address_export_from_the_ram_dp_ram_from_mm => ram_dp_ram_from_mm_mosi.address(c_dp_ram_mm_adr_w-1 DOWNTO 0),
coe_read_export_from_the_ram_dp_ram_from_mm => ram_dp_ram_from_mm_mosi.rd,
coe_readdata_export_to_the_ram_dp_ram_from_mm => ram_dp_ram_from_mm_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_ram_dp_ram_from_mm => ram_dp_ram_from_mm_mosi.wr,
coe_writedata_export_from_the_ram_dp_ram_from_mm => ram_dp_ram_from_mm_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_dp_split
coe_clk_export_from_the_reg_dp_split => OPEN,
coe_reset_export_from_the_reg_dp_split => OPEN,
coe_address_export_from_the_reg_dp_split => reg_dp_split_mosi.address(c_reg_dp_split_adr_w-1 DOWNTO 0),
coe_read_export_from_the_reg_dp_split => reg_dp_split_mosi.rd,
coe_readdata_export_to_the_reg_dp_split => reg_dp_split_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_dp_split => reg_dp_split_mosi.wr,
coe_writedata_export_from_the_reg_dp_split => reg_dp_split_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_dp_pkt_merge
coe_clk_export_from_the_reg_dp_pkt_merge => OPEN,
coe_reset_export_from_the_reg_dp_pkt_merge => OPEN,
coe_address_export_from_the_reg_dp_pkt_merge => reg_dp_pkt_merge_mosi.address(c_reg_dp_pkt_merge_adr_w-1 DOWNTO 0),
coe_read_export_from_the_reg_dp_pkt_merge => reg_dp_pkt_merge_mosi.rd,
coe_readdata_export_to_the_reg_dp_pkt_merge => reg_dp_pkt_merge_miso.rddata(c_word_w-1 DOWNTO 0),
coe_write_export_from_the_reg_dp_pkt_merge => reg_dp_pkt_merge_mosi.wr,
coe_writedata_export_from_the_reg_dp_pkt_merge => reg_dp_pkt_merge_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_dp_offload_tx
coe_address_export_from_the_reg_dp_offload_tx => reg_dp_offload_tx_mosi.address(0),
coe_clk_export_from_the_reg_dp_offload_tx => OPEN,
coe_read_export_from_the_reg_dp_offload_tx => reg_dp_offload_tx_mosi.rd,
coe_readdata_export_to_the_reg_dp_offload_tx => reg_dp_offload_tx_miso.rddata(c_word_w-1 DOWNTO 0),
coe_reset_export_from_the_reg_dp_offload_tx => OPEN,
coe_write_export_from_the_reg_dp_offload_tx => reg_dp_offload_tx_mosi.wr,
coe_writedata_export_from_the_reg_dp_offload_tx => reg_dp_offload_tx_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_dp_offload_tx_hdr_dat
coe_address_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.address(c_reg_dp_offload_tx_hdr_dat_adr_w-1 DOWNTO 0),
coe_clk_export_from_the_reg_dp_offload_tx_hdr_dat => OPEN,
coe_read_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.rd,
coe_readdata_export_to_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
coe_reset_export_from_the_reg_dp_offload_tx_hdr_dat => OPEN,
coe_write_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.wr,
coe_writedata_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
-- the_reg_tr_10GbE -- the_reg_tr_10GbE
coe_clk_export_from_the_reg_tr_10GbE => OPEN, coe_clk_export_from_the_reg_tr_10GbE => OPEN,
coe_reset_export_from_the_reg_tr_10GbE => OPEN, coe_reset_export_from_the_reg_tr_10GbE => OPEN,
......
applications/apertif/designs/apertif_unb1_fn_bf_emu/tb/vhdl/tb_apertif_unb1_fn_bf_emu.vhd
+ 4
− 18
View file @ f248d57e
...@@ -75,7 +75,6 @@ ARCHITECTURE tb OF tb_apertif_unb1_fn_bf_emu IS ...@@ -75,7 +75,6 @@ ARCHITECTURE tb OF tb_apertif_unb1_fn_bf_emu IS
SIGNAL sens_scl : STD_LOGIC; SIGNAL sens_scl : STD_LOGIC;
SIGNAL sens_sda : STD_LOGIC; SIGNAL sens_sda : STD_LOGIC;
SIGNAL si_fn_0_tx : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL si_fn_0_tx : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL fn_bn_0_tx : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS => '0');
-- Signals to interface with the DDR3 memory model. -- Signals to interface with the DDR3 memory model.
SIGNAL phy_in : t_tech_ddr3_phy_in_arr(0 DOWNTO 0); SIGNAL phy_in : t_tech_ddr3_phy_in_arr(0 DOWNTO 0);
...@@ -114,12 +113,10 @@ BEGIN ...@@ -114,12 +113,10 @@ BEGIN
u_apertif_unb1_fn_bf_emu : ENTITY work.apertif_unb1_fn_bf_emu u_apertif_unb1_fn_bf_emu : ENTITY work.apertif_unb1_fn_bf_emu
GENERIC MAP ( GENERIC MAP (
g_design_name => "fn_bf_emu", --"apertif_unb1_fn_bf_emu"; g_design_name => "fn_bf_emu", --"apertif_unb1_fn_bf_emu";
g_design_note => "Apertif subband beamformer", --"UNUSED"; g_design_note => "Apertif bf emu", --"UNUSED";
g_sim => c_sim, g_sim => c_sim,
g_sim_unb_nr => c_unb_nr, g_sim_unb_nr => c_unb_nr,
g_sim_node_nr => c_node_nr, g_sim_node_nr => c_node_nr
g_bf => c_bf,
g_use_bf => TRUE
) )
PORT MAP ( PORT MAP (
-- GENERAL -- GENERAL
...@@ -144,23 +141,12 @@ BEGIN ...@@ -144,23 +141,12 @@ BEGIN
-- Transceiver clocks -- Transceiver clocks
SA_CLK => sa_clk, -- : IN STD_LOGIC; -- SerDes Clock BN-BI / SI_FN SA_CLK => sa_clk, -- : IN STD_LOGIC; -- SerDes Clock BN-BI / SI_FN
SB_CLK => sb_clk,
-- Mesh Serial I/O
FN_BN_0_RX => fn_bn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
FN_BN_1_RX => fn_bn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
FN_BN_2_RX => fn_bn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
FN_BN_3_RX => fn_bn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
-- Serial I/O -- Serial I/O
SI_FN_0_RX => si_fn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0); SI_FN_0_RX => si_fn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_1_RX => si_fn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0); SI_FN_1_RX => si_fn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_2_RX => si_fn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0); SI_FN_2_RX => si_fn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_3_RX => si_fn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0); SI_FN_3_RX => si_fn_0_tx -- : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
MB_I_in => phy_in,
MB_I_io => phy_io,
MB_I_ou => phy_ou
); );
END tb; END tb;
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