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Commit f248d57e authored by Daniel van der Schuur's avatar Daniel van der Schuur
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-Stripped down the VHDL files; 

-Fixed paths in hdllib;
-Adjusted MM width of BG in SOPC.
parent 207e5ba7
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with 89 additions and 826 deletions
applications/apertif/designs/apertif_unb1_fn_bf_emu/hdllib.cfg
+ 2
− 2
View file @ f248d57e
......@@ -11,12 +11,12 @@ synth_top_level_entity =
synth_files =
$HDL_BUILD_DIR/unb1/quartus/apertif_unb1_fn_bf_emu/sopc_apertif_unb1_fn_bf_emu.vhd
../apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_bf_emu_udp_offload.vhd
../apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer_udp_offload.vhd
src/vhdl/mmm_apertif_unb1_fn_bf_emu.vhd
src/vhdl/apertif_unb1_fn_bf_emu.vhd
test_bench_files =
tb_apertif_unb1_fn_bf_emu.vhd
tb/vhdl/tb_apertif_unb1_fn_bf_emu.vhd
modelsim_copy_files = src/hex hex
......
applications/apertif/designs/apertif_unb1_fn_bf_emu/quartus/sopc_apertif_unb1_fn_bf_emu.sopc
+ 39
− 39
View file @ f248d57e
......@@ -92,6 +92,14 @@
type = "String";
}
}
element ram_diag_bg.mem
{
datum baseAddress
{
value = "32768";
type = "long";
}
}
element reg_mdio_2.mem
{
datum baseAddress
......@@ -100,7 +108,7 @@
type = "long";
}
}
element rom_system_info.mem
element reg_wdi.mem
{
datum _lockedAddress
{
......@@ -109,19 +117,11 @@
}
datum baseAddress
{
value = "4096";
type = "long";
}
}
element ram_diag_bg.mem
{
datum baseAddress
{
value = "32768";
value = "12288";
type = "long";
}
}
element pio_system_info.mem
element rom_system_info.mem
{
datum _lockedAddress
{
......@@ -130,68 +130,68 @@
}
datum baseAddress
{
value = "0";
value = "4096";
type = "long";
}
}
element reg_wdi.mem
{
datum _lockedAddress
element reg_mdio_0.mem
{
value = "1";
type = "boolean";
}
datum baseAddress
{
value = "12288";
value = "288";
type = "long";
}
}
element reg_diag_bg.mem
element reg_mdio_1.mem
{
datum baseAddress
{
value = "256";
value = "320";
type = "long";
}
}
element pio_pps.mem
element pio_system_info.mem
{
datum _lockedAddress
{
value = "1";
type = "boolean";
}
datum baseAddress
{
value = "440";
value = "0";
type = "long";
}
}
element reg_mdio_0.mem
element pio_pps.mem
{
datum baseAddress
{
value = "288";
value = "440";
type = "long";
}
}
element reg_tr_xaui.mem
element reg_unb_sens.mem
{
datum baseAddress
{
value = "16384";
value = "224";
type = "long";
}
}
element reg_mdio_1.mem
element reg_diag_bg.mem
{
datum baseAddress
{
value = "320";
value = "256";
type = "long";
}
}
element reg_unb_sens.mem
element reg_tr_xaui.mem
{
datum baseAddress
{
value = "224";
value = "16384";
type = "long";
}
}
......@@ -388,19 +388,19 @@
type = "long";
}
}
element timer_0.s1
element pio_debug_wave.s1
{
datum baseAddress
{
value = "192";
value = "400";
type = "long";
}
}
element pio_debug_wave.s1
element timer_0.s1
{
datum baseAddress
{
value = "400";
value = "192";
type = "long";
}
}
......@@ -447,8 +447,8 @@
<parameter name="maxAdditionalLatency" value="0" />
<parameter name="projectName">apertif_unb1_fn_bf_emu.qpf</parameter>
<parameter name="sopcBorderPoints" value="true" />
<parameter name="systemHash" value="-38264576650" />
<parameter name="timeStamp" value="1432881833399" />
<parameter name="systemHash" value="-36816734619" />
<parameter name="timeStamp" value="1432887284815" />
<parameter name="useTestBenchNamingPattern" value="false" />
<module kind="clock_source" version="11.1" enabled="1" name="clk_0">
<parameter name="clockFrequency" value="25000000" />
......@@ -549,7 +549,7 @@
<parameter name="dcache_numTCDM" value="_0" />
<parameter name="dcache_lineSize" value="_32" />
<parameter name="dcache_bursts" value="false" />
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='timer_0.s1' start='0xC0' end='0xE0' /><slave name='reg_unb_sens.mem' start='0xE0' end='0x100' /><slave name='reg_diag_bg.mem' start='0x100' end='0x120' /><slave name='reg_mdio_0.mem' start='0x120' end='0x140' /><slave name='reg_mdio_1.mem' start='0x140' end='0x160' /><slave name='reg_mdio_2.mem' start='0x160' end='0x180' /><slave name='altpll_0.pll_slave' start='0x180' end='0x190' /><slave name='pio_debug_wave.s1' start='0x190' end='0x1A0' /><slave name='pio_wdi.s1' start='0x1A0' end='0x1B0' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x1B0' end='0x1B8' /><slave name='pio_pps.mem' start='0x1B8' end='0x1C0' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='reg_tr_xaui.mem' start='0x4000' end='0x6000' /><slave name='avs_eth_0.mms_ram' start='0x6000' end='0x7000' /><slave name='ram_diag_bg.mem' start='0x8000' end='0x10000' /><slave name='reg_tr_10GbE.mem' start='0x10000' end='0x18000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' /><slave name='timer_0.s1' start='0xC0' end='0xE0' /><slave name='reg_unb_sens.mem' start='0xE0' end='0x100' /><slave name='reg_diag_bg.mem' start='0x100' end='0x120' /><slave name='reg_mdio_0.mem' start='0x120' end='0x140' /><slave name='reg_mdio_1.mem' start='0x140' end='0x160' /><slave name='reg_mdio_2.mem' start='0x160' end='0x180' /><slave name='altpll_0.pll_slave' start='0x180' end='0x190' /><slave name='pio_debug_wave.s1' start='0x190' end='0x1A0' /><slave name='pio_wdi.s1' start='0x1A0' end='0x1B0' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x1B0' end='0x1B8' /><slave name='pio_pps.mem' start='0x1B8' end='0x1C0' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='reg_tr_xaui.mem' start='0x4000' end='0x6000' /><slave name='avs_eth_0.mms_ram' start='0x6000' end='0x7000' /><slave name='ram_diag_bg.mem' start='0x8000' end='0x9000' /><slave name='reg_tr_10GbE.mem' start='0x10000' end='0x18000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
<parameter name="dataAddrWidth" value="18" />
<parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
<parameter name="cpuReset" value="false" />
......@@ -833,7 +833,7 @@ q]]></parameter>
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
</module>
<module kind="avs_common_mm" version="1.0" enabled="1" name="ram_diag_bg">
<parameter name="g_adr_w" value="13" />
<parameter name="g_adr_w" value="10" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="50000000" />
</module>
......
applications/apertif/designs/apertif_unb1_fn_bf_emu/tb/vhdl/tb_apertif_unb1_fn_bf_emu.vhd
+ 4
− 18
View file @ f248d57e
......@@ -75,7 +75,6 @@ ARCHITECTURE tb OF tb_apertif_unb1_fn_bf_emu IS
SIGNAL sens_scl : STD_LOGIC;
SIGNAL sens_sda : STD_LOGIC;
SIGNAL si_fn_0_tx : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL fn_bn_0_tx : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS => '0');
-- Signals to interface with the DDR3 memory model.
SIGNAL phy_in : t_tech_ddr3_phy_in_arr(0 DOWNTO 0);
......@@ -114,12 +113,10 @@ BEGIN
u_apertif_unb1_fn_bf_emu : ENTITY work.apertif_unb1_fn_bf_emu
GENERIC MAP (
g_design_name => "fn_bf_emu", --"apertif_unb1_fn_bf_emu";
g_design_note => "Apertif subband beamformer", --"UNUSED";
g_design_note => "Apertif bf emu", --"UNUSED";
g_sim => c_sim,
g_sim_unb_nr => c_unb_nr,
g_sim_node_nr => c_node_nr,
g_bf => c_bf,
g_use_bf => TRUE
g_sim_node_nr => c_node_nr
)
PORT MAP (
-- GENERAL
......@@ -144,23 +141,12 @@ BEGIN
-- Transceiver clocks
SA_CLK => sa_clk, -- : IN STD_LOGIC; -- SerDes Clock BN-BI / SI_FN
SB_CLK => sb_clk,
-- Mesh Serial I/O
FN_BN_0_RX => fn_bn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
FN_BN_1_RX => fn_bn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
FN_BN_2_RX => fn_bn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
FN_BN_3_RX => fn_bn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
-- Serial I/O
SI_FN_0_RX => si_fn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_1_RX => si_fn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_2_RX => si_fn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_3_RX => si_fn_0_tx, -- : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
MB_I_in => phy_in,
MB_I_io => phy_io,
MB_I_ou => phy_ou
SI_FN_3_RX => si_fn_0_tx -- : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
);
END tb;
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